On Mon, Nov 18, 2024 at 8:06 PM Sumit Garg sumit.garg@linaro.org wrote:
Hi,
On Tue, 19 Nov 2024 at 07:35, Hal Feng hal.feng@starfivetech.com wrote:
Add u-boot features to the U-Boot device tree.
For follow-up work, I would suggest minimizing U-Boot specific DT bits. You can either re-use what's available in upstream DT or push U-Boot specific changes (eg. bootph-* properties etc.) upstream.
FWIW:
Acked-by: Sumit Garg sumit.garg@linaro.org
-Sumit
Sumit, with the whole series applied this U-Boot specific DT addition is confined (with exception of what I comment on below for rx delay values on VF2 1.3b) to a single include file. Looking at linux-next there is a bit of re-organization since the Framework / DeepComputing JH7110 mainboard moved more nodes out of the common file and into board specific dts. When upstream dts settles again then there will be some more work to update this anyways. Is it any blocker for you now?
Signed-off-by: Hal Feng hal.feng@starfivetech.com
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 43 +++++++++++++++++-- arch/riscv/dts/jh7110-u-boot.dtsi | 34 +++++++++++++++ 2 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 3012466b30..fac9e16fb1 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -6,6 +6,10 @@ #include "binman.dtsi" #include "jh7110-u-boot.dtsi" / {
aliases {spi0 = &qspi;};chosen { bootph-pre-ram; };@@ -27,42 +31,70 @@
&uart0 { bootph-pre-ram;
reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;};
&mmc0 { bootph-pre-ram;
compatible = "snps,dw-mshc";};
&mmc1 { bootph-pre-ram;
compatible = "snps,dw-mshc";+};
+&phy0 {
rx-internal-delay-ps = <1900>;+};
+&phy1 {
rx-internal-delay-ps = <0>;};
Hal, please drop the override of rx-internal-delay-ps on phy0 and phy1 and simply note in the cover letter that rx delay values for VisionFive2 1.3b network phy0 and phy1 now follow the upstream dts. The effort to keep things the same as existing U-Boot is appreciated, however, I think it will cause a problem here.
&qspi { bootph-pre-ram;
spi-max-frequency = <250000000>;
nor-flash@0 {
flash@0 { bootph-pre-ram;/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>; };};
+&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,<&syscrg JH7110_SYSCLK_BUS_ROOT>,<&syscrg JH7110_SYSCLK_PERH_ROOT>,<&syscrg JH7110_SYSCLK_QSPI_REF>;assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;assigned-clock-rates = <0>, <0>, <0>, <0>;+};
&sysgpio { bootph-pre-ram; };
&mmc0_pins { bootph-pre-ram;
mmc0-pins-rest {
rst-pins { bootph-pre-ram; };};
&mmc1_pins { bootph-pre-ram;
mmc1-pins0 {
clk-pins { bootph-pre-ram; };
mmc1-pins1 {
mmc-pins { bootph-pre-ram; };}; @@ -78,6 +110,9 @@ bootph-pre-ram; eeprom@50 { bootph-pre-ram;
compatible = "atmel,24c04";reg = <0x50>;pagesize = <16>; };};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 52c1d60859..21a2ab1789 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; };
timer {compatible = "riscv,timer";interrupts-extended = <&cpu0_intc 5>,<&cpu1_intc 5>,<&cpu2_intc 5>,<&cpu3_intc 5>,<&cpu4_intc 5>;};soc { bootph-pre-ram;@@ -73,10 +82,35 @@ bootph-pre-ram; };
+&gmac0_rgmii_rxin {
bootph-pre-ram;+};
&gmac0_rmii_refin { bootph-pre-ram; };
+&gmac1_rgmii_rxin {
bootph-pre-ram;+};
+&gmac1_rmii_refin {
bootph-pre-ram;+};
+&stmmac_axi_setup {
snps,wr_osr_lmt = <4>;snps,rd_osr_lmt = <4>;+};
+&gmac0 {
snps,perfect-filter-entries = <8>;+};
+&gmac1 {
snps,perfect-filter-entries = <8>;+};
&aoncrg { bootph-pre-ram; }; -- 2.43.2
-E