Marcel,
-----Original Message----- From: Marcel Ziswiler [mailto:marcel@ziswiler.com] Sent: Tuesday, August 04, 2015 1:33 AM To: Tom Warren; u-boot@lists.denx.de Cc: tomcwarren3959@gmail.com; Stephen Warren; Thierry Reding; sjg@chromium.org Subject: Re: [PATCH 2/2] Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.
On Wed, 2015-07-29 at 13:13 -0700, Tom Warren wrote:
Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20 but needs test.
Corrections to divm mask vs shift and T20/30 divN masks thanks to Marcel Ziswiler.
Signed-off-by: Tom Warren twarren@nvidia.com
While this boots on Colibri T20/T30 as well as Apalis T30 there is still something askew on T20 as e.g. USB Ethernet is more than 6 times slower than before. T30 on the other hand seems to work fine. I will try to find some time to investigate further.
Thanks. My T20/T30 boards are moth-balled, so I don't test on them. T210 USB is fine. If you can provide CAR register dumps (0x60006000 - 0x60006FFF) on T20 I can take a look.
Appreciate any testing you can do. This won't go in to u-boot-tegra until you are satisified.
Tom -- nvpublic