some Blackfin processors have an optional async memory controller which allows for up to 4 megs of memory to be mapped. sometimes these 4 megs are not enough, so people extend this by hooking up the higher address pins to GPIOs. so if you want to map 8 megs of memory, the highest address pin would be tied to a GPIO line while the remaining address pins would be hooked up like normal directly to the processor.
there are a few ways i can implement this in u-boot (and ive prototyped a couple), but the question is which way to go. i obviously dont want to pick one which will be rejected for $whatever-reason.
possibilities: - add a command to manually toggle the GPIO lines * pros: simple to implement and requires no change to existing code * cons: requires user to manually toggle the address lines. cannot access multiple flashes in a single command. not sure if this would work with different types of flashes as the CFI code would only detect the first. - have memory display / flash write commands toggle the GPIO lines * pros: user interface is transparent and not confusing by making it seem like 1 flash exists (think software raid 0). able to use 1 write command and the lower layers will automatically split it across multiple flashes. should work with multiple types of flashes. * cons: requires modification to cmd_mem.c and cfi_flash.c.
maybe someone else has other/better ideas for how to approach the issue. i didnt seem to find anything relevant from google / bundled docs / wiki. -mike