On 07/24/2018 07:21 PM, Xavier Ruppen wrote:
The ReflexCES PCIe carrier board Arria 10 SoC SoM (R329) provides access to all the features of the Arria 10 SoC SoM (R315) (Ethernet, OTG USB, Transceivers, UART) and adds further functions, including SFP+ connectors, PCIe x8 Gen3, USB3.0 and a wifi interface.
No fpga portion is provided in fit_spl_fpga.its as MSEL is hardwired on this board. Thus, a bitstream is loaded before booting by using the EPCQ. It is possible to load a bitstream from the HPS (packaged in the .sfp file) but a small hardware mod on the MSEL lines is required (tested and works).
Signed-off-by: Xavier Ruppen xruppen@gmail.com Cc: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dinh Nguyen dinguyen@kernel.org
This patch was created and tested against u-boot-socfpga/arria10_sdmmc.
Can it be based on u-boot/master and does it work ? I am not accepting patches on top of these random branches.
The handoff.dtsi file was created by meld'ing the (old) .dts file provided by ReflexCES and socfpga_arria10_socdk_sdmmc_handoff.dtsi.
The board was tested with what I believe is the factory bitstream written in the EPCQ.
As I copied and pasted the majority of the files from the arria10-socdk, I purposely ignored a bunch of checkpatch warnings, i.e. lenghty lines and a missing SPDX-License-Identifier in the .dts(i) files.
Those should be fixed ...
[...]
+++ b/include/configs/socfpga_r329_a10_pcie.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
- */
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__
+#include <asm/arch/base_addr_a10.h>
+/* Booting Linux */ +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/*
- U-Boot general configurations
- */
+/* Cache options */ +#define CONFIG_SYS_DCACHE_OFF
Is this needed ?
+/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0xC0000000
+/* Ethernet on SoC (EMAC) */
The comments need cleanup.
+/*
- U-Boot environment configurations
- */
+/*
- Serial / UART configurations
- */
+#define CONFIG_SYS_NS16550_MEM32
Needed ?
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Needed ?
If so, should be enabled on all socfpgas .
+/*
- L4 OSC1 Timer 0
- */
+/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF
+/*
- Flash configurations
- */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h>
+#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */