On 09/26/2016 01:13 AM, Zhiqiang Hou wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
This patch map the sys_info->freq_systembus to Platform PLL, and implement the IPs' clock function individually.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Generate the patch set base on the latest git://git.denx.de/u-boot-fsl-qoriq.git.
- Add Platform clock and IPs' input clock divisors.
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 31 ++++++++++++++++------ arch/arm/include/asm/arch-fsl-layerscape/config.h | 8 ++++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + include/configs/ls2080a_common.h | 2 +- 4 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a9b12a4..afc8a31 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -88,11 +88,10 @@ void get_sys_info(struct sys_info *sys_info) #endif #endif
- /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
- /* Platform clock is half of platform PLL */
- sys_info->freq_systembus /= 2; sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -132,7 +131,8 @@ void get_sys_info(struct sys_info *sys_info) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
- sys_info->freq_localbus = sys_info->freq_systembus / ccr;
- sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_PCLK_DIV / ccr;#endif }
Zhiqiang and Prabhakar,
Your patches collide with each other. Can you two work together to sort it out?
http://patchwork.ozlabs.org/patch/666849/
York