Re: [U-Boot] [PATCH v2 08/20] arm: socfpga: Add clock driver for Arria 10

On 03/09/2017 01:26 AM, Ley Foon Tan wrote:

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com

---

arch/arm/mach-socfpga/Makefile | 3 +- arch/arm/mach-socfpga/clock_manager.c | 18 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 1104 ++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 + .../include/mach/clock_manager_arria10.h | 222 ++++ 5 files changed, 1350 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index d81f003..c494930 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,8 @@ obj-y += misc.o timer.o reset_manager.o clock_manager.o \ fpga_manager.o board.o

-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \

• 			reset_manager_arria10.o
  
  

obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index c2af6f3..ad602c8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -5,6 +5,8 @@ */

#include <common.h> +#include <fdtdec.h> +#include <wait_bit.h> #include <asm/io.h> #include <asm/arch/clock_manager.h>

@@ -18,7 +20,12 @@ void cm_wait_for_lock(u32 mask) u32 inter_val; u32 retry = 0; do { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

• inter_val = readl(&clock_manager_base->stat) & mask;
  

+#endif

• /* Wait for stable lock */
  

  if (inter_val == mask) retry++; else

@@ -31,8 +38,10 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ void cm_wait_for_fsm(void) {

• while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)

• ;
  

• wait_for_bit(__func__, (const u32 *)&clock_manager_base->stat,

•      CLKMGR_CLKMGR_STAT_BUSY_SET_MSK,
  

•      false, 20000, false);
  

Please do test this change on CV or AV if you didn't already.

}

int set_cpu_clk_info(void) @@ -43,7 +52,12 @@ int set_cpu_clk_info(void)

gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

• gd->bd->bi_ddr_freq = 0;

+#endif

return 0; } diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c new file mode 100644 index 0000000..67b3e58 --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -0,0 +1,1104 @@ +/*

• • Copyright (C) 2016-2017 Intel Corporation
• • SPDX-License-Identifier: GPL-2.0
• */

+#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include <asm/arch/clock_manager.h>

+DECLARE_GLOBAL_DATA_PTR;

+static u32 eosc1_hz; +static u32 cb_intosc_hz; +static u32 f2s_free_hz; +static u32 cm_l4_main_clk_hz; +static u32 cm_l4_sp_clk_hz; +static u32 cm_l4_mp_clk_hz; +static u32 cm_l4_sys_free_clk_hz;

+struct mainpll_cfg {

• u32 vco0_psrc;
• u32 vco1_denom;
• u32 vco1_numer;
• u32 mpuclk;
• u32 mpuclk_cnt;
• u32 mpuclk_src;
• u32 nocclk;
• u32 nocclk_cnt;
• u32 nocclk_src;
• u32 cntr2clk_cnt;
• u32 cntr3clk_cnt;
• u32 cntr4clk_cnt;
• u32 cntr5clk_cnt;
• u32 cntr6clk_cnt;
• u32 cntr7clk_cnt;
• u32 cntr7clk_src;
• u32 cntr8clk_cnt;
• u32 cntr9clk_cnt;
• u32 cntr9clk_src;
• u32 cntr15clk_cnt;
• u32 nocdiv_l4mainclk;
• u32 nocdiv_l4mpclk;
• u32 nocdiv_l4spclk;
• u32 nocdiv_csatclk;
• u32 nocdiv_cstraceclk;
• u32 nocdiv_cspdbclk;

+};

+struct perpll_cfg {

• u32 vco0_psrc;
• u32 vco1_denom;
• u32 vco1_numer;
• u32 cntr2clk_cnt;
• u32 cntr2clk_src;
• u32 cntr3clk_cnt;
• u32 cntr3clk_src;
• u32 cntr4clk_cnt;
• u32 cntr4clk_src;
• u32 cntr5clk_cnt;
• u32 cntr5clk_src;
• u32 cntr6clk_cnt;
• u32 cntr6clk_src;
• u32 cntr7clk_cnt;
• u32 cntr8clk_cnt;
• u32 cntr8clk_src;
• u32 cntr9clk_cnt;
• u32 emacctl_emac0sel;
• u32 emacctl_emac1sel;
• u32 emacctl_emac2sel;
• u32 gpiodiv_gpiodbclk;

+};

+struct alteragrp_cfg {

• u32 nocclk;
• u32 mpuclk;

+};

+static const struct socfpga_clock_manager *clock_manager_base =

• (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

+static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg) +{

• if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",

• 		 (u32 *)cfg, cfg_len)) {
  

• /* could not find required property */
  

• return -EINVAL;
  

• }
• return 0;

+}

+static int of_get_input_clks(const void *blob, int node, u32 *val) +{

• *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
• if (!*val)

• return -EINVAL;
  

• return 0;

+}

+static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,

• 	  struct perpll_cfg *per_cfg,
  

• 	  struct alteragrp_cfg *altrgrp_cfg)
  

+{

• int node, child, len;
• const char *node_name;
• node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK);
• if (node < 0)

• return -EINVAL;
  

• child = fdt_first_subnode(blob, node);
• if (child < 0)

• return -EINVAL;
  

• child = fdt_first_subnode(blob, child);
• if (child < 0)

• return -EINVAL;
  

• node_name = fdt_get_name(blob, child, &len);
• while (node_name) {

• if (!strcmp(node_name, "osc1")) {
  

• 	if (of_get_input_clks(blob, child, &eosc1_hz))
  

• 		return -EINVAL;
  

• } else if (!strcmp(node_name, "cb_intosc_ls_clk")) {
  

• 	if (of_get_input_clks(blob, child, &cb_intosc_hz))
  

• 		return -EINVAL;
  

• } else if (!strcmp(node_name, "f2s_free_clk")) {
  

• 	if (of_get_input_clks(blob, child, &f2s_free_hz))
  

• 		return -EINVAL;
  

• } else if (!strcmp(node_name, "main_pll")) {
  

• 	if (of_to_struct(blob, child,
  

• 			 sizeof(*main_cfg)/sizeof(u32),
  

• 			 main_cfg))
  

• 		return -EINVAL;
  

• } else if (!strcmp(node_name, "periph_pll")) {
  

• 	if (of_to_struct(blob, child,
  

• 			 sizeof(*per_cfg)/sizeof(u32),
  

• 			 per_cfg))
  

• 		return -EINVAL;
  

• } else if (!strcmp(node_name, "altera")) {
  

• 	if (of_to_struct(blob, child,
  

• 			 sizeof(*altrgrp_cfg)/sizeof(u32),
  

• 			 altrgrp_cfg))
  

• 		return -EINVAL;
  

• 	main_cfg->mpuclk = altrgrp_cfg->mpuclk;
  

• 	main_cfg->nocclk = altrgrp_cfg->nocclk;
  

• }
  

• child = fdt_next_subnode(blob, child);
  

• if (child < 0)
  

• 	break;
  

• node_name = fdt_get_name(blob, child, &len);
  

• }
• return 0;

+}

+/* calculate the intended main VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_main_vco_clk_hz

• 			(struct mainpll_cfg *main_cfg)
  

+{

• unsigned int clk_hz;
• /* Check main VCO clock source: eosc, intosc or f2s? */
• switch (main_cfg->vco0_psrc) {
• case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:

• clk_hz = eosc1_hz;
  

• break;
  

• case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:

• clk_hz = cb_intosc_hz;
  

• break;
  

• case CLKMGR_MAINPLL_VCO0_PSRC_F2S:

• clk_hz = f2s_free_hz;
  

• break;
  

• default:

• return 0;
  

• }
• /* calculate the VCO frequency */
• clk_hz /= (1 + main_cfg->vco1_denom);
• clk_hz *= (1 + main_cfg->vco1_numer);
• return clk_hz;

+}

+/* calculate the intended periph VCO frequency based on handoff */ +static unsigned int cm_calc_handoff_periph_vco_clk_hz(

• struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
  

+{

• unsigned int clk_hz;
• /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
• switch (per_cfg->vco0_psrc) {
• case CLKMGR_PERPLL_VCO0_PSRC_EOSC:

• clk_hz = eosc1_hz;
  

• break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:

• clk_hz = cb_intosc_hz;
  

• break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_F2S:

• clk_hz = f2s_free_hz;
  

• break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_MAIN:

• clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
  

• clk_hz /= main_cfg->cntr15clk_cnt;
  

• break;
  

• default:

• return 0;
  

• }
• /* calculate the VCO frequency */
• clk_hz /= (1 + per_cfg->vco1_denom);
• clk_hz *= (1 + per_cfg->vco1_numer);

Extra parenthesis around statement not needed, fix globally.

• return clk_hz;

+}

+/* calculate the intended MPU clock frequency based on handoff */ +static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,

• 			       struct perpll_cfg *per_cfg)
  

+{

• unsigned int clk_hz;
• /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
• switch (main_cfg->mpuclk_src) {
• case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:

• clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
  

• clk_hz /= ((main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
  

• 	   + 1);
  

DTTO

• break;
  

• case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:

• clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
  

• clk_hz /= (((main_cfg->mpuclk >>
  

• 	   CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
  

• 	   CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
  

DTTO

• break;
  

• case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:

• clk_hz = eosc1_hz;
  

• break;
  

• case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:

• clk_hz = cb_intosc_hz;
  

• break;
  

• case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:

• clk_hz = f2s_free_hz;
  

• break;
  

• default:

• return 0;
  

• }
• clk_hz /= (main_cfg->mpuclk_cnt + 1);
• return clk_hz;

+}

+/* calculate the intended NOC clock frequency based on handoff */ +static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,

• 			       struct perpll_cfg *per_cfg)
  

+{

• unsigned int clk_hz;
• /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
• switch (main_cfg->nocclk_src) {
• case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:

• clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
  

• clk_hz /= ((main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
  

• 	   + 1);
  

DTTO

• break;
  

• case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:

• clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
  

• clk_hz /= (((main_cfg->nocclk >>
  

• 	   CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
  

• 	   CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1);
  

DTTO

• break;
  

• case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:

• clk_hz = eosc1_hz;
  

• break;
  

• case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:

• clk_hz = cb_intosc_hz;
  

• break;
  

• case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:

• clk_hz = f2s_free_hz;
  

• break;
  

• default:

• return 0;
  

• }
• clk_hz /= (main_cfg->nocclk_cnt + 1);
• return clk_hz;

+}

+/* return 1 if PLL ramp is required */ +static int cm_is_pll_ramp_required(int main0periph1,

• 		   struct mainpll_cfg *main_cfg,
  

• 		   struct perpll_cfg *per_cfg)
  

+{

• /* Check for main PLL */
• if (main0periph1 == 0) {

• /*
  

•  * PLL ramp is not required if both MPU clock and NOC clock are
  

•  * not sourced from main PLL
  

•  */
  

• if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
  

•     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
  

• 	return 0;
  

• /*
  

•  * PLL ramp is required if MPU clock is sourced from main PLL
  

•  * and MPU clock is over 900MHz (as advised by HW team)
  

•  */
  

• if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
  

•     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
  

•      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
  

• 	return 1;
  

• /*
  

•  * PLL ramp is required if NOC clock is sourced from main PLL
  

•  * and NOC clock is over 300MHz (as advised by HW team)
  

•  */
  

• if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
  

•     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
  

•      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
  

• 	return 2;
  

• } else if (main0periph1 == 1) {

• /*
  

•  * PLL ramp is not required if both MPU clock and NOC clock are
  

•  * not sourced from periph PLL
  

•  */
  

• if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
  

•     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
  

• 	return 0;
  

• /*
  

•  * PLL ramp is required if MPU clock are source from periph PLL
  

•  * and MPU clock is over 900MHz (as advised by HW team)
  

•  */
  

• if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
  

•     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
  

•      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
  

• 	return 1;
  

• /*
  

•  * PLL ramp is required if NOC clock are source from periph PLL
  

•  * and NOC clock is over 300MHz (as advised by HW team)
  

•  */
  

• if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
  

•     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
  

•      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
  

• 	return 2;
  

• }
• return 0;

+}

+/*

• • Calculate the new PLL numerator which is based on existing DTS hand off and
• • intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
• • numerator while maintaining denominator as denominator will influence the
• • jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
• • value for numerator is minus with 1 to cater our register value
• • representation.
• */

+static unsigned int cm_calc_safe_pll_numer(int main0periph1,

• 			   struct mainpll_cfg *main_cfg,
  

• 			   struct perpll_cfg *per_cfg,
  

• 			   unsigned int safe_hz)
  

+{

• unsigned int clk_hz = 0;
• /* Check for main PLL */
• if (main0periph1 == 0) {

• /* Check main VCO clock source: eosc, intosc or f2s? */
  

• switch (main_cfg->vco0_psrc) {
  

• case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
  

• 	clk_hz = eosc1_hz;
  

• 	break;
  

• case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
  

• 	clk_hz = cb_intosc_hz;
  

• 	break;
  

• case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
  

• 	clk_hz = f2s_free_hz;
  

• 	break;
  

• default:
  

• 	return 0;
  

• }
  

• /* Applicable if MPU clock is from main PLL */
  

• if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
  

• 	/* calculate the safe numer value */
  

• 	clk_hz = (safe_hz / clk_hz) *
  

• 		(main_cfg->mpuclk_cnt + 1) *
  

• 		((main_cfg->mpuclk &
  

• 		  CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
  

• 		(1 + main_cfg->vco1_denom) - 1;
  

Maybe you can factor out this awful equation into a function somehow ?

• }
  

• /* Reach here if MPU clk not from main PLL but NOC clk is */
  

• else if (main_cfg->nocclk_src ==
  

• 	 CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
  

• 	/* calculate the safe numer value */
  

• 	clk_hz = (safe_hz / clk_hz) *
  

• 		(main_cfg->nocclk_cnt + 1) *
  

• 		((main_cfg->nocclk &
  

• 		  CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
  

• 		(1 + main_cfg->vco1_denom) - 1;
  

• } else
  

• 	clk_hz = 0;
  

• } else if (main0periph1 == 1) {

• /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
  

• switch (per_cfg->vco0_psrc) {
  

• case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
  

• 	clk_hz = eosc1_hz;
  

• 	break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
  

• 	clk_hz = cb_intosc_hz;
  

• 	break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_F2S:
  

• 	clk_hz = f2s_free_hz;
  

• 	break;
  

• case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
  

• 	clk_hz = cm_calc_handoff_main_vco_clk_hz(
  

• 		 main_cfg);
  

• 	clk_hz /= main_cfg->cntr15clk_cnt;
  

• 	break;
  

• default:
  

• 	return 0;
  

• }
  

• /* Applicable if MPU clock is from periph PLL */
  

• if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
  

• 	/* calculate the safe numer value */
  

• 	clk_hz = (safe_hz / clk_hz) *
  

• 		(main_cfg->mpuclk_cnt + 1) *
  

• 		(((main_cfg->mpuclk >>
  

• 		  CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
  

• 		  CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1) *
  

• 		(1 + per_cfg->vco1_denom) - 1;
  

• }
  

• /* Reach here if MPU clk not from periph PLL but NOC clk is */
  

• else if (main_cfg->nocclk_src ==
  

• 	 CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
  

• 	/* calculate the safe numer value */
  

• 	clk_hz = (safe_hz / clk_hz) *
  

• 		(main_cfg->nocclk_cnt + 1) *
  

• 		(((main_cfg->nocclk >>
  

• 		  CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
  

• 		  CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1) *
  

• 		(1 + per_cfg->vco1_denom) - 1;
  

• } else
  

• 	clk_hz = 0;
  

• }
• return clk_hz;

+}

[...]

+unsigned int cm_get_per_vco_clk_hz(void) +{

• u32 src_hz = 0;
• u32 clk_src = 0;
• u32 numer = 0;
• u32 denom = 0;
• u32 vco = 0;
• clk_src = readl(&clock_manager_base->per_pll.vco0);
• clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) &

• CLKMGR_PERPLL_VCO0_PSRC_MSK;
  

• if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) {

• src_hz = eosc1_hz;
  

• } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {

• src_hz = cb_intosc_hz;
  

• } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) {

• src_hz = f2s_free_hz;
  

• } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) {

• src_hz = cm_get_main_vco_clk_hz();
  

• src_hz /= (readl
  

• 	(&clock_manager_base->main_pll.cntr15clk) &
  

• 	CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
  

• } else {

• printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src);
  

• return 0;
  

• }
• vco = readl(&clock_manager_base->per_pll.vco1);
• numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK;
• denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &

• 	CLKMGR_PERPLL_VCO1_DENOM_MSK;
  

• vco = src_hz;
• vco /= (1 + denom);
• vco *= (1 + numer);

Extra parenthesis, not needed ...

• return vco;

+}

+unsigned int cm_get_main_vco_clk_hz(void) +{

• u32 src_hz, numer, denom, vco;
• u32 clk_src = readl(&clock_manager_base->main_pll.vco0);
• clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) &

• CLKMGR_MAINPLL_VCO0_PSRC_MSK;
  

• if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {

• src_hz = eosc1_hz;
  

• } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {

• src_hz = cb_intosc_hz;
  

• } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) {

• src_hz = f2s_free_hz;
  

• } else {

• printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src);
  

• return 0;
  

• }
• vco = readl(&clock_manager_base->main_pll.vco1);
• numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
• denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &

• 	CLKMGR_MAINPLL_VCO1_DENOM_MSK;
  

• vco = src_hz;
• vco /= (1 + denom);
• vco *= (1 + numer);

DTTO

btw this function looks just like the previous one ...

• return vco;

+}

+unsigned int cm_get_l4_sp_clk_hz(void) +{

• return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB);

+}

+unsigned int cm_get_mmc_controller_clk_hz(void) +{

• u32 clk_hz = 0;
• u32 clk_input = 0;
• clk_input = readl(&clock_manager_base->per_pll.cntr6clk);
• clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &

• CLKMGR_PERPLLGRP_SRC_MSK;
  

• switch (clk_input) {
• case CLKMGR_PERPLLGRP_SRC_MAIN:

• clk_hz = cm_get_main_vco_clk_hz();
  

• clk_hz /= 1 +
  

• 	(readl
  

• 	(&clock_manager_base->main_pll.cntr6clk) &
  

• 	CLKMGR_MAINPLL_CNTRCLK_MSK);
  

• break;
  

• case CLKMGR_PERPLLGRP_SRC_PERI:

• clk_hz = cm_get_per_vco_clk_hz();
  

• clk_hz /= 1 + (readl
  

• 	(&clock_manager_base->per_pll.cntr6clk) &
  

• 	CLKMGR_PERPLL_CNTRCLK_MSK);
  

• break;
  

• case CLKMGR_PERPLLGRP_SRC_OSC1:

• clk_hz = eosc1_hz;
  

• break;
  

• case CLKMGR_PERPLLGRP_SRC_INTOSC:

• clk_hz = cb_intosc_hz;
  

• break;
  

• case CLKMGR_PERPLLGRP_SRC_FPGA:

• clk_hz = f2s_free_hz;
  

• break;
  

• }
• return clk_hz / 4;

+}

+unsigned int cm_get_spi_controller_clk_hz(void) +{

• return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);

+}

+unsigned int cm_get_qspi_controller_clk_hz(void) +{

• return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);

+}

+void cm_print_clock_quick_summary(void) +{

• printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
• printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
• printf("QSPI %8d kHz\n",

•       cm_get_qspi_controller_clk_hz() / 1000);
  

• printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
• printf("EOSC1 %8d kHz\n", eosc1_hz / 1000);
• printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000);
• printf("f2s_free %8d kHz\n", f2s_free_hz / 1000);
• printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000);
• printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000);
• printf("L4 Main %8d kHz\n",

•       cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000);
  

• printf("L4 MP %8d kHz\n",

•       cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
  

• printf("L4 SP %8d kHz\n",

•       cm_get_l4_sp_clk_hz() / 1000);
  

• printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000);

This should be part of the clock command ... see CV clock command.

+} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index d0d0487..ec067ae 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -13,7 +13,13 @@ void cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void); #endif

+/* Common mask */ +#define CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001

BIT(0) ?

#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <asm/arch/clock_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/clock_manager_arria10.h> #endif

#endif /* _CLOCK_MANAGER_H_ */

[...]

+/* mask */ +#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040

Looks more like a BIT() to me ...

+#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080 +#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100 +#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200 +#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000 +#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004 +#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 +#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002 +#define CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004 +#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 +#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 +#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800 +#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400 +#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200 +#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100 +#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008 +#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004 +#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001 +#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002 +#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001 +#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300 +#define CLKMGR_PERPLL_EN_RESET 0x00000f7f +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020 +#define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003 +#define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff +#define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f +#define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4 +#define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003 +#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff +#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007 +#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0 +#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1 +#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2 +#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3 +#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4

+#define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007 +#define CLKMGR_PERPLLGRP_SRC_MAIN 0 +#define CLKMGR_PERPLLGRP_SRC_PERI 1 +#define CLKMGR_PERPLLGRP_SRC_OSC1 2 +#define CLKMGR_PERPLLGRP_SRC_INTOSC 3 +#define CLKMGR_PERPLLGRP_SRC_FPGA 4

+/* bit shifting macro */ +#define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_PERPLL_VCO0_PSRC_LSB 8 +#define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_PERPLL_VCO1_DENOM_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 +#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 +#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 +#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 +#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 +#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 +#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16 +#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16 +#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16 +#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 +#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 +#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28

+/* PLL ramping work around */ +#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000 +#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000 +#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000 +#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000

+#endif /* CLOCK_MANAGER_ARRIA10 */