
25 Nov
2014
25 Nov
'14
6:52 p.m.
On 10/16/2014 08:42 PM, Nikhil Badola wrote:
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes
Signed-off-by: Nikhil Badola nikhil.badola@freescale.com
Depends on patch https://patchwork.ozlabs.org/patch/394797/
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/usb/host/ehci-fsl.c | 3 +-- include/fsl_usb.h | 11 +++++++++++ 4 files changed, 17 insertions(+), 2 deletions(-)
Applied to u-boot-fsl-qoriq master. Awaiting upstream. Thanks.
York