On Tuesday, December 02, 2014 at 02:26:14 PM, Stefan Roese wrote:
This patch adds support for multiple NAND chips connected to the i.MX6. Linux already supports this configuration. So lets port the missing features to the U-Boot driver to support more than one NAND chip here as well.
The necessary changes in detail are:
- Only use DMA channel 0 for all NAND chips: Linux: a7c12d01 (mtd: gpmi: use DMA channel 0 for all the nand chips) d159d8b7 (mtd: gpmi: decouple the chip select from the DMA channel)
- On i.MX6 only use ready/busy pin for CS0: Linux: 7caa4fd2 (mtd: gpmi: imx6: fix the wrong method for checking ready/busy)
To enable this feature the board needs to configure CONFIG_SYS_NAND_MAX_CHIPS to 2 (or more).
With these changes I'm able to detect and acces 2 NAND chips:
=> nand device
Device 0: 2x nand0, sector size 128 KiB Page size 2048 b OOB size 64 b Erase size 131072 b
Shouldn't you see "Device 0" and "Device 1" ?
Please note that this is also needed to support a NAND chip with multiple chips embedded in one die, e.g. Micron MT29F32G08QAA.
Tested on a i.MX6DL based board with 2 Micron MT29F4G08AB chips.
Signed-off-by: Stefan Roese sr@denx.de Cc: Marek Vasut marex@denx.de Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam fabio.estevam@freescale.com Cc: Scott Wood scottwood@freescale.com
Looks pretty trivial, thanks!
Reviewed-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut