On 06/25 11:55, Simon Glass wrote:
The SPI flash starts off protected on baytrail. The code which is supposed to fix this is broken. This series fixes that, enables the SPI environment and adds documentation.
Also when driver model is enabled for PCI some bugs appear. This series fixes those and enables driver model for PCI on minnowboard MAX.
Changes in v2:
- Continue to use writew for ICH7
- Use ich_read/write() for BIOS protection update
- Fix typos in README.x86
- Rename the ops and ids arrays for consistency
- Drop the coreboot PCI driver which is no-longer needed
- Only limit the PCI system memory region on x86 machines
Simon Glass (7): dm: spi: Correct status register access width dm: spi: Correct BIOS protection logic for ICH9 dm: spi: Enable environment for minnowmax x86: Add ROM image description for minnowmax x86: pci: Tidy up the generic x86 PCI driver dm: x86: minnowmax: Move PCI to use driver model dm: x86: baytrail: Correct PCI region 3 when driver model is used
arch/x86/cpu/baytrail/Makefile | 1 - arch/x86/cpu/baytrail/pci.c | 46 --------------------------------------- arch/x86/cpu/coreboot/pci.c | 21 ------------------ arch/x86/cpu/cpu.c | 1 + arch/x86/dts/minnowmax.dts | 10 +++++++++ common/board_f.c | 4 ++++ configs/minnowmax_defconfig | 1 + doc/README.x86 | 17 +++++++++++++++ drivers/pci/pci-uclass.c | 8 +++++-- drivers/pci/pci_x86.c | 13 ++++++----- drivers/spi/ich.c | 15 ++++++++----- include/asm-generic/global_data.h | 1 + include/configs/minnowmax.h | 6 ++--- 13 files changed, 60 insertions(+), 84 deletions(-) delete mode 100644 arch/x86/cpu/baytrail/pci.c
Tested-by: Andrew Bradford andrew.bradford@kodakalaris.com
I don't actually have a Minnowmax board or any E3800 board that has the type of SPI flash that's on Minnowmax, but when I try to do an `env save` it just seems to hang unless I interrupt it with ^C (output below). Even waiting 15 minutes for the env write to complete doesn't help (I don't currently have a logic analyzer hooked up, sorry).
I'm running the minnowmax_defconfig but adjusted only to handle that I have a SODIMM installed so telling FSP to set memory_down to 0 (hence 1 GB of memory). My board is close enough to Minnow Max to be useful (patches to support it hopefully coming real soon now).
But the PCI bits seem to be working for me! :)
Thanks! -Andrew
Output from doing `env save`:
U-Boot 2015.07-rc2-00176-gc3dd276 (Jun 29 2015 - 08:17:03 -0400)
CPU: x86_64, vendor Intel, device 30679h DRAM: 1 GiB Warning: MP init failure MMC: ValleyView SDHCI: 0, ValleyView SDHCI: 1 SF: Detected W25Q64DW with page size 256 Bytes, erase size 4 KiB, total 8 MiB, mapped at ff800000 *** Warning - bad CRC, using default environment
Video: 1280x1024x16 Model: Intel Minnowboard Max SCSI: SATA link 0 timeout. SATA link 1 timeout. AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode flags: 64bit ncq stag pm led clo pio slum part sxs scanning bus for devices... Found 0 device(s). Net: RTL8169#0 Error: RTL8169#0 address not set.
=> env print baudrate=115200 bootargs=root=/dev/sdb3 init=/sbin/init rootwait ro bootcmd=ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000 bootfile=bzImage consoledev=ttyS0 ethact=RTL8169#0 hostname="x86" loadaddr=0x1000000 netdev=eth0 nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftpboot $loadaddr $bootfile;zboot $loadaddr othbootargs=acpi=off pciconfighost=1 ramboot=setenv bootargs root=/dev/ram rw ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftpboot $loadaddr $bootfile;tftpboot $ramdiskaddr $ramdiskfile;zboot $loadaddr 0 $ramdiskaddr $filesize ramdiskaddr=0x2000000 ramdiskfile=initramfs.gz rootpath=/opt/nfsroot scsidevs=0 stderr=vga,serial stdin=usbkbd,vga,serial stdout=vga,serial
Environment size: 920/4092 bytes => env set simon says => env save Saving Environment to SPI Flash... SF: Detected W25Q64DW with page size 256 Bytes, erase size 4 KiB, total 8 MiB, mapped at ff800000 Erasing SPI flash...Writing to SPI flash...=> <INTERRUPT> =>