Re: [PATCH v4 5/8] rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit

30 Oct 2020

On 2020/10/28 下午9:33, Jagan Teki wrote:
...
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board from Engicam.
PX30.Core needs to mount on top of this Evaluation board for
creating complete PX30.Core EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
Signed-off-by: Suniel Mahesh sunil@amarulasolutions.com
Reviewed-by: Kever Yangkever.yang@rock-chips.com
Thanks,
- Kever
...

Changes for v4:

drop ram change

on top of https://patchwork.ozlabs.org/project/uboot/patch/20201001184003.3704604-1-he...
arch/arm/dts/Makefile                     |   1 +
arch/arm/dts/px30-px30-core-edimm2.2.dts  |  21 +++++
arch/arm/mach-rockchip/px30/Kconfig       |  10 ++
board/engicam/px30_core/Kconfig           |  16 ++++
board/engicam/px30_core/MAINTAINERS       |   7 ++
board/engicam/px30_core/Makefile          |   7 ++
board/engicam/px30_core/px30_core.c       |   4 +
configs/px30-core-edimm2.2-px30_defconfig | 108 ++++++++++++++++++++++
include/configs/px30_core.h               |  15 +++
9 files changed, 189 insertions(+)
create mode 100644 arch/arm/dts/px30-px30-core-edimm2.2.dts
create mode 100644 board/engicam/px30_core/Kconfig
create mode 100644 board/engicam/px30_core/MAINTAINERS
create mode 100644 board/engicam/px30_core/Makefile
create mode 100644 board/engicam/px30_core/px30_core.c
create mode 100644 configs/px30-core-edimm2.2-px30_defconfig
create mode 100644 include/configs/px30_core.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f16..b87f4334a5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -72,6 +72,7 @@ dtb-$(CONFIG_MACH_S700) += \
  dtb-$(CONFIG_ROCKCHIP_PX30) += \
   px30-evb.dtb \
   px30-firefly.dtb \

px30-px30-core-edimm2.2.dtb \
rk3326-odroid-go2.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \


diff --git a/arch/arm/dts/px30-px30-core-edimm2.2.dts b/arch/arm/dts/px30-px30-core-edimm2.2.dts
new file mode 100644
index 0000000000..c36280ce7f
--- /dev/null
+++ b/arch/arm/dts/px30-px30-core-edimm2.2.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*


Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd



Copyright (c) 2020 Engicam srl



Copyright (c) 2020 Amarula Solutions(India)


*/


+/dts-v1/;
+#include "px30.dtsi"
+#include "px30-engicam-edimm2.2.dtsi"
+#include "px30-px30-core.dtsi"



+/ {

model = "Engicam PX30.Core EDIMM2.2 Starter Kit";
compatible = "engicam,px30-core-edimm2.2", "engicam,px30-px30-core",
     "rockchip,px30";



chosen {
stdout-path = "serial2:115200n8";


};

+};
diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig
index 6cd65dfa97..5d014f6561 100644
--- a/arch/arm/mach-rockchip/px30/Kconfig
+++ b/arch/arm/mach-rockchip/px30/Kconfig
@@ -11,6 +11,15 @@ config TARGET_EVB_PX30
  config TARGET_ODROID_GO2
   bool "ODROID_GO2"
+config TARGET_PX30_CORE

bool "Engicam PX30.Core"
help
 PX30.Core EDIMM2.2:


 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.


 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.


 * PX30.Core needs to mount on top of EDIMM2.2 for creating complete


   PX30.Core EDIMM2.2 Starter Kit.


config ROCKCHIP_BOOT_MODE_REG
 default 0xff010200

@@ -44,6 +53,7 @@ config DEBUG_UART_CHANNEL
     For using the UART for early debugging the route to use needs
     to be declared (0 or 1).
+source "board/engicam/px30_core/Kconfig"
  source "board/hardkernel/odroid_go2/Kconfig"
  source "board/rockchip/evb_px30/Kconfig"
diff --git a/board/engicam/px30_core/Kconfig b/board/engicam/px30_core/Kconfig
new file mode 100644
index 0000000000..a03be78369
--- /dev/null
+++ b/board/engicam/px30_core/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_PX30_CORE



+config SYS_BOARD

default "px30_core"


+config SYS_VENDOR

default "engicam"


+config SYS_CONFIG_NAME

default "px30_core"


+config BOARD_SPECIFIC_OPTIONS # dummy

def_bool y
select RAM_PX30_DDR4


+endif
diff --git a/board/engicam/px30_core/MAINTAINERS b/board/engicam/px30_core/MAINTAINERS
new file mode 100644
index 0000000000..f98a84450a
--- /dev/null
+++ b/board/engicam/px30_core/MAINTAINERS
@@ -0,0 +1,7 @@
+PX30-Core-EDIMM2.2
+M:	Jagan Teki jagan@amarulasolutions.com
+M:	Suniel Mahesh sunil@amarulasolutions.com
+S:	Maintained
+F:	board/engicam/px30_core
+F:	include/configs/px30_core.h
+F:	configs/px30-core-edimm2.2-px30_defconfig
diff --git a/board/engicam/px30_core/Makefile b/board/engicam/px30_core/Makefile
new file mode 100644
index 0000000000..321fdb0173
--- /dev/null
+++ b/board/engicam/px30_core/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#



+obj-y	+= px30_core.o
diff --git a/board/engicam/px30_core/px30_core.c b/board/engicam/px30_core/px30_core.c
new file mode 100644
index 0000000000..3adc2f11de
--- /dev/null
+++ b/board/engicam/px30_core/px30_core.c
@@ -0,0 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*


Copyright (c) 2020 Amarula Solutions(India)


*/

diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
new file mode 100644
index 0000000000..50a9a150c8
--- /dev/null
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_TEXT_BASE=0x00000000
+CONFIG_ROCKCHIP_PX30=y
+CONFIG_TARGET_PX30_CORE=y
+CONFIG_DEBUG_UART_CHANNEL=1
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEBUG_UART_BASE=0xFF160000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="px30-px30-core-edimm2.2"
+CONFIG_DEBUG_UART=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x600
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/px30-px30-core-edimm2.2.dtb"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+# CONFIG_TPL_BANNER_PRINT is not set
+CONFIG_SPL_CRC32_SUPPORT=y
+CONFIG_SPL_ATF=y
+# CONFIG_TPL_FRAMEWORK is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_ROCKCHIP_SDRAM_COMMON=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+# CONFIG_SPECIFY_CONSOLE_INDEX is not set
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_SOUND=y
+CONFIG_SYSRESET=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_LCD=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
+CONFIG_LZO=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/px30_core.h b/include/configs/px30_core.h
new file mode 100644
index 0000000000..01b4995598
--- /dev/null
+++ b/include/configs/px30_core.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*


Copyright (c) 2020 Amarula Solutions(India)


*/


+#ifndef __PX30_CORE_H
+#define __PX30_CORE_H



+#include <configs/px30_common.h>



+#define ROCKCHIP_DEVICE_SETTINGS \

"stdout=serial,vidconsole\0" \


"stderr=serial,vidconsole\0"




+#endif /* __PX30_CORE_H */

    