On Tue, Jul 22, 2014 at 2:08 PM, Daniel Drake drake@endlessm.com wrote:
While looking at the old uboot from hardkernel, I'm curious about CONFIG_CLK_BUS_DMC_220_440, which is set by default. This appears to run the memory at a high speed, by writing certain registers in the Dynamic Memory Controller (e.g. TIMINGROW), and clocking MPLL to 880MHz.
Your uboot patches don't seem to touch DMC regs like TIMINGROW, and also clock the MPLL at 800MHz.
I looked in more detail, and now understand better the SPL vs uboot division.
The vendor code I was referring to above is SPL code.
Since we are still using the same SPL as before, it means that MPLL and memory is already set up by the time the real/new uboot loads.
So I think there should be no need to modify MPLL, and I wonder if most of the other clock configuration code in your patches is also unnecessary.
Thoughts?
Thanks Daniel