Until now the clkctrl clocks have been enabled/disabled through platform routines. Thanks to this patch they can be enabled and configured directly by the probed devices that need to use them.
Signed-off-by: Dario Binacchi dariobin@libero.it ---
doc/device-tree-bindings/clock/ti,clkctrl.txt | 61 +++++++++++ drivers/clk/Kconfig | 6 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-ti-ctrl.c | 102 ++++++++++++++++++ 4 files changed, 170 insertions(+) create mode 100644 doc/device-tree-bindings/clock/ti,clkctrl.txt create mode 100644 drivers/clk/clk-ti-ctrl.c
diff --git a/doc/device-tree-bindings/clock/ti,clkctrl.txt b/doc/device-tree-bindings/clock/ti,clkctrl.txt new file mode 100644 index 0000000000..0f73f6295a --- /dev/null +++ b/doc/device-tree-bindings/clock/ti,clkctrl.txt @@ -0,0 +1,61 @@ +Texas Instruments clkctrl clock binding + +Texas Instruments SoCs can have a clkctrl clock controller for each +interconnect target module. The clkctrl clock controller manages functional +and interface clocks for each module. Each clkctrl controller can also +gate one or more optional functional clocks for a module, and can have one +or more clock muxes. There is a clkctrl clock controller typically for each +interconnect target module on omap4 and later variants. + +The clock consumers can specify the index of the clkctrl clock using +the hardware offset from the clkctrl instance register space. The optional +clocks can be specified by clkctrl hardware offset and the index of the +optional clock. + +For more information, please see the Linux clock framework binding at +doc/device-tree-bindings/clock/clock-bindings.txt. + +Required properties : +- compatible : shall be "ti,clkctrl" or a clock domain specific name: + "ti,clkctrl-l4-cfg" + "ti,clkctrl-l4-per" + "ti,clkctrl-l4-secure" + "ti,clkctrl-l4-wkup" +- #clock-cells : shall contain 2 with the first entry being the instance + offset from the clock domain base and the second being the + clock index +- reg : clock registers + +Example: Clock controller node on omap 4430: + +&cm2 { + l4per: cm@1400 { + cm_l4per@0 { + cm_l4per_clkctrl: clock@20 { + compatible = "ti,clkctrl-l4-per", "ti,clkctrl"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; + }; +}; + +Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h + +#define OMAP4_CLKCTRL_OFFSET 0x20 +#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) +#define MODULEMODE_HWCTRL 1 +#define MODULEMODE_SWCTRL 2 + +#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) +#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) +#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) +... +#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) + +Example: Clock consumer node for GPIO2: + +&gpio2 { + clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 + &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; +}; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c0528c2aeb..90c953667a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -105,6 +105,12 @@ config CLK_TI_AM3_DPLL This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL provides all interface clocks and functional clocks to the processor.
+config CLK_TI_CTRL + bool "TI OMAP4 clock controller" + depends on CLK && OF_CONTROL + help + This enables the clock controller driver support on TI's SoCs. + config CLK_TI_DIVIDER bool "TI divider clock driver" depends on CLK && OF_CONTROL && CLK_CCF diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 4d16fb7a50..cdc3102ad7 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-ti-am3-dpll.o clk-ti-am3-dpll-x2.o +obj-$(CONFIG_CLK_TI_CTRL) += clk-ti-ctrl.o obj-$(CONFIG_CLK_TI_DIVIDER) += clk-ti-divider.o obj-$(CONFIG_CLK_TI_GATE) += clk-ti-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-ti-mux.o diff --git a/drivers/clk/clk-ti-ctrl.c b/drivers/clk/clk-ti-ctrl.c new file mode 100644 index 0000000000..ed0a2ee7d1 --- /dev/null +++ b/drivers/clk/clk-ti-ctrl.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP clock controller support + * + * Copyright (C) 2020 Dario Binacchi dariobin@libero.it + */ + +#include <common.h> +#include <dm.h> +#include <clk-uclass.h> +#include <asm/arch-am33xx/clock.h> + +struct clk_ti_ctrl_priv { + fdt_addr_t regs; + fdt_size_t regs_size; +}; + +static int clk_ti_ctrl_disable(struct clk *clk) +{ + struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); + u32 *clk_modules[2] = { }; + + if (clk->id >= priv->regs_size) + return -EINVAL; + + clk_modules[0] = (u32 *)(priv->regs + clk->id); + dev_dbg(dev, "module address=%p\n", clk_modules[0]); + do_disable_clocks(NULL, clk_modules, 1); + return 0; +} + +static int clk_ti_ctrl_enable(struct clk *clk) +{ + struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev); + u32 *clk_modules[2] = { }; + + if (clk->id >= priv->regs_size) + return -EINVAL; + + clk_modules[0] = (u32 *)(priv->regs + clk->id); + dev_dbg(dev, "module address=%p\n", clk_modules[0]); + do_enable_clocks(NULL, clk_modules, 1); + return 0; +} + +static ulong clk_ti_ctrl_get_rate(struct clk *clk) +{ + return 0; +} + +static int clk_ti_ctrl_of_xlate(struct clk *clk, + struct ofnode_phandle_args *args) +{ + if (args->args_count != 2) { + dev_err(dev, "invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + clk->id = args->args[0]; + else + clk->id = 0; + + dev_dbg(dev, "name=%s, id=%ld\n", clk->dev->name, clk->id); + return 0; +} + +static int clk_ti_ctrl_ofdata_to_platdata(struct udevice *dev) +{ + struct clk_ti_ctrl_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_size_index(dev, 0, &priv->regs_size); + if (priv->regs == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get control registers\n"); + return -EINVAL; + } + + dev_dbg(dev, "regs=0x%08lx, size=0x%08lx\n", priv->regs, + priv->regs_size); + return 0; +} + +static struct clk_ops clk_ti_ctrl_ops = { + .of_xlate = clk_ti_ctrl_of_xlate, + .enable = clk_ti_ctrl_enable, + .disable = clk_ti_ctrl_disable, + .get_rate = clk_ti_ctrl_get_rate, +}; + +static const struct udevice_id clk_ti_ctrl_ids[] = { + {.compatible = "ti,clkctrl"}, + {}, +}; + +U_BOOT_DRIVER(clk_ti_ctrl) = { + .name = "ti_ctrl_clk", + .id = UCLASS_CLK, + .of_match = clk_ti_ctrl_ids, + .ofdata_to_platdata = clk_ti_ctrl_ofdata_to_platdata, + .ops = &clk_ti_ctrl_ops, + .priv_auto_alloc_size = sizeof(struct clk_ti_ctrl_priv), +};