From: Tien Fong Chee tien.fong.chee@intel.com
This patchset adding FPGA drivers, SDRAM drivers, and generic firmware loader. The patchset also enable fpga loadfs to program FPGA, SPL loading U-boot and booting to U-boot console. This version mainly resolved comments from Marek in [v4].
Please note that generic firmware loader is an independent driver, which can be used to load whatever into target location, then consumer driver would use it to program whatever, ie. the FPGA.
This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socfpga.git .
[v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg268160.html
v4 -> v5 changes: ----------------- - Created generic firmware loader which is very similar to Linux firmware loader - Changed the fpga loadfs driver to use generic firmware loader for loading RBF files from flash to memory and then program FPGA.
Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg261831.html [v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg265192.html [v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg266981.html
Tien Fong Chee (20): ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager dts: Add FPGA bitstream properties to Arria 10 DTS arm: socfpga: Add Arria 10 SoCFPGA programming interface dts: Enable fpga-mgr node build for Arria 10 SPL fs: Enable generic filesystems interface support in SPL. arm: socfpga: Remove static declaration on spl_mmc_find_device function common: Generic firmware loader for file system arm: socfpga: Fix with the correct polling on bit is set arm: socfpga: Add FPGA drivers for Arria 10 FPGA loadfs arm: socfpga: Rename the gen5 sdram driver to more specific name arm: socfpga: Add DRAM bank size initialization function arm: socfpga: Add DDR driver for Arria 10 configs: Add DDR Kconfig support for Arria 10 arm: socfpga: Enable SPL memory allocation arm: socfpga: Improve comments for Intel SoCFPGA program header arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 arm: socfpga: Adding clock frequency info for U-Boot arm: socfpga: Adding SoCFPGA info for both SPL and U-Boot arm: socfpga: Enable DDR working arm: socfpga: Enable SPL booting U-boot
arch/arm/dts/socfpga_arria10.dtsi | 6 + arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-socfpga/board.c | 18 + arch/arm/mach-socfpga/include/mach/boot0.h | 11 +- .../include/mach/fpga_manager_arria10.h | 32 + arch/arm/mach-socfpga/include/mach/sdram.h | 434 +----------- arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + .../include/mach/{sdram.h => sdram_gen5.h} | 6 +- arch/arm/mach-socfpga/misc_arria10.c | 5 - arch/arm/mach-socfpga/spl.c | 49 ++ cmd/fpga.c | 2 +- common/Makefile | 1 + common/fs_loader.c | 304 +++++++++ common/spl/Kconfig | 8 + common/spl/spl_mmc.c | 2 +- configs/socfpga_arria10_defconfig | 58 +- doc/README.SPL | 1 + .../fpga/altera-socfpga-a10-fpga-mgr.txt | 11 + drivers/ddr/altera/Kconfig | 2 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_arria10.c | 733 +++++++++++++++++++++ drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0 drivers/fpga/altera.c | 40 +- drivers/fpga/fpga.c | 8 + drivers/fpga/socfpga_arria10.c | 378 ++++++++++- fs/Makefile | 1 + include/altera.h | 6 + include/configs/socfpga_common.h | 23 +- include/fpga.h | 2 + include/fs_loader.h | 30 + include/spl.h | 2 + 31 files changed, 1716 insertions(+), 463 deletions(-) copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%) create mode 100644 common/fs_loader.c create mode 100644 drivers/ddr/altera/sdram_arria10.c rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%) create mode 100644 include/fs_loader.h