AT91CAP9 support - include/ files
Signed-off-by: Stelian Pop stelian@popies.net --- include/asm-arm/arch-at91cap9/AT91CAP9.h | 529 ++++++++++++++++++++++++++++ include/asm-arm/arch-at91cap9/clk.h | 38 ++ include/asm-arm/arch-at91cap9/hardware.h | 38 ++ include/asm-arm/arch-at91cap9/memory-map.h | 34 ++ include/asm-arm/dma-mapping.h | 50 +++ 5 files changed, 689 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/arch-at91cap9/AT91CAP9.h create mode 100644 include/asm-arm/arch-at91cap9/clk.h create mode 100644 include/asm-arm/arch-at91cap9/hardware.h create mode 100644 include/asm-arm/arch-at91cap9/memory-map.h create mode 100644 include/asm-arm/dma-mapping.h
diff --git a/include/asm-arm/arch-at91cap9/AT91CAP9.h b/include/asm-arm/arch-at91cap9/AT91CAP9.h new file mode 100644 index 0000000..f0d7cc2 --- /dev/null +++ b/include/asm-arm/arch-at91cap9/AT91CAP9.h @@ -0,0 +1,529 @@ +/* + * (C) Copyright 2008 + * AT91CAP9 definitions + * Author : ATMEL AT91 application group + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91CAP9_H +#define AT91CAP9_H + +typedef volatile unsigned int AT91_REG; + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller Interface +// ***************************************************************************** +typedef struct _AT91S_SMC { + AT91_REG SMC_SETUP0; // Setup Register for CS 0 + AT91_REG SMC_PULSE0; // Pulse Register for CS 0 + AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 + AT91_REG SMC_CTRL0; // Control Register for CS 0 + AT91_REG SMC_SETUP1; // Setup Register for CS 1 + AT91_REG SMC_PULSE1; // Pulse Register for CS 1 + AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 + AT91_REG SMC_CTRL1; // Control Register for CS 1 + AT91_REG SMC_SETUP2; // Setup Register for CS 2 + AT91_REG SMC_PULSE2; // Pulse Register for CS 2 + AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 + AT91_REG SMC_CTRL2; // Control Register for CS 2 + AT91_REG SMC_SETUP3; // Setup Register for CS 3 + AT91_REG SMC_PULSE3; // Pulse Register for CS 3 + AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 + AT91_REG SMC_CTRL3; // Control Register for CS 3 + AT91_REG SMC_SETUP4; // Setup Register for CS 4 + AT91_REG SMC_PULSE4; // Pulse Register for CS 4 + AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 + AT91_REG SMC_CTRL4; // Control Register for CS 4 + AT91_REG SMC_SETUP5; // Setup Register for CS 5 + AT91_REG SMC_PULSE5; // Pulse Register for CS 5 + AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 + AT91_REG SMC_CTRL5; // Control Register for CS 5 + AT91_REG SMC_SETUP6; // Setup Register for CS 6 + AT91_REG SMC_PULSE6; // Pulse Register for CS 6 + AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 + AT91_REG SMC_CTRL6; // Control Register for CS 6 + AT91_REG SMC_SETUP7; // Setup Register for CS 7 + AT91_REG SMC_PULSE7; // Pulse Register for CS 7 + AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 + AT91_REG SMC_CTRL7; // Control Register for CS 7 +} AT91S_SMC, *AT91PS_SMC; + +// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- +#define AT91C_SMC_NWESETUP ((unsigned int) 0x3F << 0) // (SMC) NWE Setup Length +#define AT91C_SMC_NCSSETUPWR ((unsigned int) 0x3F << 8) // (SMC) NCS Setup Length in WRite Access +#define AT91C_SMC_NRDSETUP ((unsigned int) 0x3F << 16) // (SMC) NRD Setup Length +#define AT91C_SMC_NCSSETUPRD ((unsigned int) 0x3F << 24) // (SMC) NCS Setup Length in ReaD Access +// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- +#define AT91C_SMC_NWEPULSE ((unsigned int) 0x7F << 0) // (SMC) NWE Pulse Length +#define AT91C_SMC_NCSPULSEWR ((unsigned int) 0x7F << 8) // (SMC) NCS Pulse Length in WRite Access +#define AT91C_SMC_NRDPULSE ((unsigned int) 0x7F << 16) // (SMC) NRD Pulse Length +#define AT91C_SMC_NCSPULSERD ((unsigned int) 0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access +// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- +#define AT91C_SMC_NWECYCLE ((unsigned int) 0x1FF << 0) // (SMC) Total Write Cycle Length +#define AT91C_SMC_NRDCYCLE ((unsigned int) 0x1FF << 16) // (SMC) Total Read Cycle Length +// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- +#define AT91C_SMC_READMODE ((unsigned int) 0x1 << 0) // (SMC) Read Mode +#define AT91C_SMC_WRITEMODE ((unsigned int) 0x1 << 1) // (SMC) Write Mode +#define AT91C_SMC_NWAITM ((unsigned int) 0x3 << 5) // (SMC) NWAIT Mode +#define AT91C_SMC_NWAITM_NWAIT_DISABLE ((unsigned int) 0x0 << 5) // (SMC) External NWAIT disabled. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN ((unsigned int) 0x2 << 5) // (SMC) External NWAIT enabled in frozen mode. +#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY ((unsigned int) 0x3 << 5) // (SMC) External NWAIT enabled in ready mode. +#define AT91C_SMC_BAT ((unsigned int) 0x1 << 8) // (SMC) Byte Access Type +#define AT91C_SMC_BAT_BYTE_SELECT ((unsigned int) 0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. +#define AT91C_SMC_BAT_BYTE_WRITE ((unsigned int) 0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. +#define AT91C_SMC_DBW ((unsigned int) 0x3 << 12) // (SMC) Data Bus Width +#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS ((unsigned int) 0x0 << 12) // (SMC) 8 bits. +#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS ((unsigned int) 0x1 << 12) // (SMC) 16 bits. +#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS ((unsigned int) 0x2 << 12) // (SMC) 32 bits. +#define AT91C_SMC_TDF ((unsigned int) 0xF << 16) // (SMC) Data Float Time. +#define AT91C_SMC_TDFEN ((unsigned int) 0x1 << 20) // (SMC) TDF Enabled. +#define AT91C_SMC_PMEN ((unsigned int) 0x1 << 24) // (SMC) Page Mode Enabled. +#define AT91C_SMC_PS ((unsigned int) 0x3 << 28) // (SMC) Page Size +#define AT91C_SMC_PS_SIZE_FOUR_BYTES ((unsigned int) 0x0 << 28) // (SMC) 4 bytes. +#define AT91C_SMC_PS_SIZE_EIGHT_BYTES ((unsigned int) 0x1 << 28) // (SMC) 8 bytes. +#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES ((unsigned int) 0x2 << 28) // (SMC) 16 bytes. +#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES ((unsigned int) 0x3 << 28) // (SMC) 32 bytes. +// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- +// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- +// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- +// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- +// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR AHB CCFG Interface +// ***************************************************************************** +typedef struct _AT91S_CCFG { + AT91_REG Reserved0[1]; // + AT91_REG CCFG_MPBS0; // Slave 1 (MP Block Slave 0) Special Function Register + AT91_REG CCFG_UDPHS; // Slave 2 (AHB Periphs) Special Function Register + AT91_REG CCFG_MPBS1; // Slave 3 (MP Block Slave 1) Special Function Register + AT91_REG CCFG_EBICSA; // EBI Chip Select Assignement Register + AT91_REG Reserved1[2]; // + AT91_REG CCFG_MPBS2; // Slave 7 (MP Block Slave 2) Special Function Register + AT91_REG CCFG_MPBS3; // Slave 7 (MP Block Slave 3) Special Function Register + AT91_REG CCFG_BRIDGE; // Slave 8 (APB Bridge) Special Function Register + AT91_REG Reserved2[49]; // + AT91_REG CCFG_MATRIXVERSION;// Version Register +} AT91S_CCFG, *AT91PS_CCFG; + +// -------- CCFG_UDPHS : (CCFG Offset: 0x8) UDPHS Configuration -------- +#define AT91C_CCFG_UDPHS_UDP_SELECT ((unsigned int) 0x1 << 31) // (CCFG) UDPHS or UDP Selection +#define AT91C_CCFG_UDPHS_UDP_SELECT_UDPHS ((unsigned int) 0x0 << 31) // (CCFG) UDPHS Selected. +#define AT91C_CCFG_UDPHS_UDP_SELECT_UDP ((unsigned int) 0x1 << 31) // (CCFG) UDP Selected. +// -------- CCFG_EBICSA : (CCFG Offset: 0x10) EBI Chip Select Assignement Register -------- +#define AT91C_EBI_CS1A ((unsigned int) 0x1 << 1) // (CCFG) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC ((unsigned int) 0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_BCRAMC ((unsigned int) 0x1 << 1) // (CCFG) Chip Select 1 is assigned to the BCRAM Controller. +#define AT91C_EBI_CS3A ((unsigned int) 0x1 << 3) // (CCFG) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC ((unsigned int) 0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. +#define AT91C_EBI_CS3A_SM ((unsigned int) 0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. +#define AT91C_EBI_CS4A ((unsigned int) 0x1 << 4) // (CCFG) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC ((unsigned int) 0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. +#define AT91C_EBI_CS4A_CF ((unsigned int) 0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. +#define AT91C_EBI_CS5A ((unsigned int) 0x1 << 5) // (CCFG) Chip Select 5 Assignment +#define AT91C_EBI_CS5A_SMC ((unsigned int) 0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC +#define AT91C_EBI_CS5A_CF ((unsigned int) 0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. +#define AT91C_EBI_DBPUC ((unsigned int) 0x1 << 8) // (CCFG) Data Bus Pull-up Configuration +#define AT91C_EBI_DDRPUC ((unsigned int) 0x1 << 9) // (CCFG) DDDR DQS Pull-up Configuration +#define AT91C_EBI_SUP ((unsigned int) 0x1 << 16) // (CCFG) EBI Supply +#define AT91C_EBI_SUP_1V8 ((unsigned int) 0x0 << 16) // (CCFG) EBI Supply is 1.8V +#define AT91C_EBI_SUP_3V3 ((unsigned int) 0x1 << 16) // (CCFG) EBI Supply is 3.3V +#define AT91C_EBI_LP ((unsigned int) 0x1 << 17) // (CCFG) EBI Low Power Reduction +#define AT91C_EBI_LP_LOW_DRIVE ((unsigned int) 0x0 << 17) // (CCFG) EBI Pads are in Standard drive +#define AT91C_EBI_LP_STD_DRIVE ((unsigned int) 0x1 << 17) // (CCFG) EBI Pads are in Low Drive (Low Power) +#define AT91C_CCFG_DDR_SDR_SELECT ((unsigned int) 0x1 << 31) // (CCFG) DDR or SDR Selection +#define AT91C_CCFG_DDR_SDR_SELECT_DDR ((unsigned int) 0x0 << 31) // (CCFG) DDR Selected. +#define AT91C_CCFG_DDR_SDR_SELECT_SDR ((unsigned int) 0x1 << 31) // (CCFG) SDR Selected. +// -------- CCFG_BRIDGE : (CCFG Offset: 0x24) BRIDGE Configuration -------- +#define AT91C_CCFG_AES_TDES_SELECT ((unsigned int) 0x1 << 31) // (CCFG) AES or TDES Selection +#define AT91C_CCFG_AES_TDES_SELECT_AES ((unsigned int) 0x0 << 31) // (CCFG) AES Selected. +#define AT91C_CCFG_AES_TDES_SELECT_TDES ((unsigned int) 0x1 << 31) // (CCFG) TDES Selected. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG PMC_UCKR; // UTMI Clock Configuration Register + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG PMC_PLLAR; // PLL A Register + AT91_REG PMC_PLLBR; // PLL B Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved1[3]; // + AT91_REG PMC_PCKR[8]; // Programmable Clock Register + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; + +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_OTG ((unsigned int) 0x1 << 5) // (PMC) USB OTG Clock +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- +// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is four times faster than the master clock +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask +#define AT91C_PMC_LOCKU ((unsigned int) 0x1 << 6) // (PMC) PLL UTMI Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; + +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset +#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_GENERAL ((unsigned int) 0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. +#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; + +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; + +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// -------- SPI_PTCR : PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91CAP9 +// ***************************************************************************** +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_SPI0_MISO ((unsigned int) AT91C_PIO_PA0) +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_SPI0_MOSI ((unsigned int) AT91C_PIO_PA1) +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_SPI0_SPCK ((unsigned int) AT91C_PIO_PA2) +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA3) +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_SPI0_NPCS2A ((unsigned int) AT91C_PIO_PA4) +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA5) +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 +#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD0 ((unsigned int) AT91C_PIO_PA22) +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_RXD0 ((unsigned int) AT91C_PIO_PA23) +#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_SPI0_NPCS3A ((unsigned int) AT91C_PIO_PA28) +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_E_TXCK ((unsigned int) AT91C_PIO_PB21) +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_E_RXDV ((unsigned int) AT91C_PIO_PB22) +#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_E_TX0 ((unsigned int) AT91C_PIO_PB23) +#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_E_TX1 ((unsigned int) AT91C_PIO_PB24) +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_E_RX0 ((unsigned int) AT91C_PIO_PB25) +#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_E_RX1 ((unsigned int) AT91C_PIO_PB26) +#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_E_RXER ((unsigned int) AT91C_PIO_PB27) +#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_E_TXEN ((unsigned int) AT91C_PIO_PB28) +#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_E_MDC ((unsigned int) AT91C_PIO_PB29) +#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_E_MDIO ((unsigned int) AT91C_PIO_PB30) +#define AT91C_PIO_PB31 ((unsigned int) 1 << 31) // Pin Controlled by PB31 +#define AT91C_PIO_PC29 ((unsigned int) 1 << 29) // Pin Controlled by PC29 +#define AT91C_PIO_PC30 ((unsigned int) 1 << 30) // Pin Controlled by PC30 +#define AT91C_PC30_DRXD ((unsigned int) AT91C_PIO_PC30) +#define AT91C_PIO_PC31 ((unsigned int) 1 << 31) // Pin Controlled by PC31 +#define AT91C_PC31_DTXD ((unsigned int) AT91C_PIO_PC31) +#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) // Pin Controlled by PD0 +#define AT91C_PD0_TXD1 ((unsigned int) AT91C_PIO_PD0) +#define AT91C_PD0_SPI0_NPCS2D ((unsigned int) AT91C_PIO_PD0) +#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) // Pin Controlled by PD1 +#define AT91C_PD1_RXD1 ((unsigned int) AT91C_PIO_PD1) +#define AT91C_PD1_SPI0_NPCS3D ((unsigned int) AT91C_PIO_PD1) +#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) // Pin Controlled by PD2 +#define AT91C_PD2_TXD2 ((unsigned int) AT91C_PIO_PD2) +#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) // Pin Controlled by PD3 +#define AT91C_PD3_RXD2 ((unsigned int) AT91C_PIO_PD3) +#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) // Pin Controlled by PD15 + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91CAP9 +// ***************************************************************************** + +#define AT91C_ID_SYS ((unsigned int) 1) // System Controller +#define AT91C_ID_PIOABCD ((unsigned int) 2) // Parallel IO Controller A, B, C and D +#define AT91C_ID_US0 ((unsigned int) 8) // USART 0 +#define AT91C_ID_US1 ((unsigned int) 9) // USART 1 +#define AT91C_ID_US2 ((unsigned int) 10) // USART 2 +#define AT91C_ID_SPI0 ((unsigned int) 15) // Serial Peripheral Interface 0 +#define AT91C_ID_EMAC ((unsigned int) 22) // Ethernet Mac +#define AT91C_ID_UHP ((unsigned int) 29) // USB Host Port + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91CAP9 +// ***************************************************************************** +#define AT91C_BASE_SMC ((AT91PS_SMC) 0xFFFFE800) // (SMC) Base Address +#define AT91C_BASE_CCFG ((AT91PS_CCFG) 0xFFFFEB10) // (CCFG) Base Address +#define AT91C_BASE_DBGU ((unsigned long) 0xFFFFEE00) // (DBGU) Base Address +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF200) // (PIOA) Base Address +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF400) // (PIOB) Base Address +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF600) // (PIOC) Base Address +#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFF800) // (PIOD) Base Address +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_US0 ((unsigned long) 0xFFF8C000) // (US0) Base Address +#define AT91C_BASE_US1 ((unsigned long) 0xFFF90000) // (US1) Base Address +#define AT91C_BASE_US2 ((unsigned long) 0xFFF94000) // (US2) Base Address +#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFA4000) // (SPI0) Base Address +#define AT91C_BASE_MACB ((unsigned long) 0xFFFBC000) // (MACB) Base Address + +#endif diff --git a/include/asm-arm/arch-at91cap9/clk.h b/include/asm-arm/arch-at91cap9/clk.h new file mode 100644 index 0000000..3bdff45 --- /dev/null +++ b/include/asm-arm/arch-at91cap9/clk.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2007 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_CLK_H__ +#define __ASM_ARM_ARCH_CLK_H__ + +#include <asm/arch/hardware.h> + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return AT91C_MASTER_CLOCK; +} + +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return AT91C_MASTER_CLOCK; +} +#endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91cap9/hardware.h b/include/asm-arm/arch-at91cap9/hardware.h new file mode 100644 index 0000000..3d2566b --- /dev/null +++ b/include/asm-arm/arch-at91cap9/hardware.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2007 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> + +#include <asm/arch/AT91CAP9.h> + +/** + * container_of - cast a member of a structure out to the containing structure + * + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#endif diff --git a/include/asm-arm/arch-at91cap9/memory-map.h b/include/asm-arm/arch-at91cap9/memory-map.h new file mode 100644 index 0000000..4e8694f --- /dev/null +++ b/include/asm-arm/arch-at91cap9/memory-map.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_MEMORYMAP_H__ +#define __ASM_ARM_ARCH_MEMORYMAP_H__ + +#include <asm/arch/AT91CAP9.h> + +#define USART0_BASE AT91C_BASE_US0 +#define USART1_BASE AT91C_BASE_US1 +#define USART2_BASE AT91C_BASE_US2 +#define USART3_BASE AT91C_BASE_DBGU + +#endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h new file mode 100644 index 0000000..800ce18 --- /dev/null +++ b/include/asm-arm/dma-mapping.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2007 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARM_DMA_MAPPING_H +#define __ASM_ARM_DMA_MAPPING_H + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; + +static void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)malloc(len); + return (void *)*handle; +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_ARM_DMA_MAPPING_H */