Re: [U-Boot] [PATCH 1/3 v8] arm926ejs: add NXP LPC32x0 cpu series support

This change adds initial support for NXP LPC32x0 SoC series.

Signed-off-by: Vladimir Zapolskiy vz@mleia.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Wolfgang Denk wd@denx.de

---

Quick skim looks fine:

Acked-by: Marek Vasut marek.vasut@gmail.com

Changes from v7 to v8:

• renamed register structures from *_t to *_regs
• renamed clkpwr.c file to clk.c
• fixed several macro definitions
• various cosmetic fixes

Changes from v6 to v7:

• get use of setbits_le32() and friends
• add arch_cpu_init() routine

Changes from v5 to v6:

• replaced some spaces with tabs in macro declarations
• more rules separating 14-clock and ns16650 UARTs in config.h

Changes from v4 to v5:

• corrected address in GPLv2+ licence header in files

Changes from v3 to v4:

• extended memory controller definitions are introduced
• added print_cpuinfo() function

Changes from v2 to v3:

• checkpatch.pl reports zero errors and warnings

Changes from v1 to v2:

• BIT(n) and SBF(s, v) macro are not used anymore
• removed NS16550 and 14-clock UART definitions from uart.h
• added devices.c file, which contains standard UART preinitialization

routine * added get_serial_clock() function, it returns actual frequency of UART clock * __udelay() realization is simplified, no need of interrupt handling

arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 45 +++++++ arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 117 +++++++++++++++++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 70 ++++++++++ arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 52 ++++++++ arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 90 +++++++++++++ arch/arm/include/asm/arch-lpc32xx/clk.h | 170 +++++++++++++++++++++++++ arch/arm/include/asm/arch-lpc32xx/config.h | 76 +++++++++++ arch/arm/include/asm/arch-lpc32xx/cpu.h | 64 +++++++++ arch/arm/include/asm/arch-lpc32xx/emc.h | 92 +++++++++++++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 25 ++++ arch/arm/include/asm/arch-lpc32xx/timer.h | 74 +++++++++++ arch/arm/include/asm/arch-lpc32xx/uart.h | 54 ++++++++ arch/arm/include/asm/arch-lpc32xx/wdt.h | 51 ++++++++ 13 files changed, 980 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/Makefile create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/clk.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/devices.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/timer.c create mode 100644 arch/arm/include/asm/arch-lpc32xx/clk.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/config.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/cpu.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/emc.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/sys_proto.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/timer.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/uart.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/wdt.h

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile new file mode 100644 index 0000000..ae1f0a5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -0,0 +1,45 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# as published by the Free Software Foundation; either version 2 +# of the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +#

+include $(TOPDIR)/config.mk

+LIB = $(obj)lib$(SOC).o

+COBJS = cpu.o clk.o devices.o timer.o

+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

+all: $(obj).depend $(LIB)

+$(LIB): $(OBJS)

• $(call cmd_link_o_target, $(OBJS))

+#########################################################################

+# defines $(obj).depend target +include $(SRCTREE)/rules.mk

+sinclude $(obj).depend

+######################################################################### diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c new file mode 100644 index 0000000..6f26d62 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -0,0 +1,117 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#include <common.h> +#include <div64.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/io.h>

+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;

+unsigned int get_sys_clk_rate(void) +{

• if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)

• return RTC_CLK_FREQUENCY * 397;
  

• else

• return OSC_CLK_FREQUENCY;
  

+}

+unsigned int get_hclk_pll_rate(void) +{

• unsigned long long fin, fref, fcco, fout;
• u32 val, m_div, n_div, p_div;
• /*

• * Valid frequency ranges:
  

• *     1 * 10^6 <=  Fin <=  20 * 10^6
  

• *     1 * 10^6 <= Fref <=  27 * 10^6
  

• *   156 * 10^6 <= Fcco <= 320 * 10^6
  

• */
  

• fref = fin = get_sys_clk_rate();
• if (fin > 20000000ULL || fin < 1000000ULL)

• return 0;
  

• val = readl(&clk->hclkpll_ctrl);
• m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
• n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
• if (val & CLK_HCLK_PLL_DIRECT)

• p_div = 0;
  

• else

• p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
  

• p_div = 1 << p_div;
• if (val & CLK_HCLK_PLL_BYPASS) {

• do_div(fin, p_div);
  

• return fin;
  

• }
• do_div(fref, n_div);
• if (fref > 27000000ULL || fref < 1000000ULL)

• return 0;
  

• fout = fref * m_div;
• if (val & CLK_HCLK_PLL_FEEDBACK) {

• fcco = fout;
  

• do_div(fout, p_div);
  

• } else

• fcco = fout * p_div;
  

• if (fcco > 320000000ULL || fcco < 156000000ULL)

• return 0;
  

• return fout;

+}

+unsigned int get_hclk_clk_div(void) +{

• u32 val;
• val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
• return 1 << val;

+}

+unsigned int get_hclk_clk_rate(void) +{

• return get_hclk_pll_rate() / get_hclk_clk_div();

+}

+unsigned int get_periph_clk_div(void) +{

• u32 val;
• val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
• return (val >> 2) + 1;

+}

+unsigned int get_periph_clk_rate(void) +{

• if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))

• return get_sys_clk_rate();
  

• return get_hclk_pll_rate() / get_periph_clk_div();

+}

+int get_serial_clock(void) +{

• return get_periph_clk_rate();

+} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c new file mode 100644 index 0000000..e29e130 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -0,0 +1,70 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/io.h>

+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;

+void reset_cpu(ulong addr) +{

• /* Enable watchdog clock */
• setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
• /* Reset pulse length is 13005 peripheral clock frames */
• writel(13000, &wdt->pulse);
• /* Force WDOG_RESET2 and RESOUT_N signal active */
• writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,

•       &wdt->mctrl);
  

• while (1)

• /* NOP */;
  

+}

+#if defined(CONFIG_ARCH_CPU_INIT) +int arch_cpu_init(void) +{

• /*

• * It might be necessary to flush data cache, if U-boot is loaded
  

• * from kickstart bootloader, e.g. from S1L loader
  

• */
  

• flush_dcache_all();
• return 0;

+} +#else +#error "You have to select CONFIG_ARCH_CPU_INIT" +#endif

+#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{

• printf("CPU: NXP LPC32XX\n");
• printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
• printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
• printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
• return 0;

+} +#endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c new file mode 100644 index 0000000..9f305b5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -0,0 +1,52 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/uart.h> +#include <asm/io.h>

+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; + +void lpc32xx_uart_init(unsigned int uart_id) +{

• if (uart_id < 1 || uart_id > 7)

• return;
  

• /* Disable loopback mode, if it is set by S1L bootloader */
• clrbits_le32(&ctrl->loop,

•      UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
  

• if (uart_id < 3 || uart_id > 6)

• return;
  

• /* Enable UART system clock */
• setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
• /* Set UART into autoclock mode */
• clrsetbits_le32(&ctrl->clkmode,

• 	UART_CLKMODE_MASK(uart_id),
  

• 	UART_CLKMODE_AUTO(uart_id));
  

• /* Bypass pre-divider of UART clock */
• writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),

•       &clk->u3clk + (uart_id - 3));
  

+} diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c new file mode 100644 index 0000000..ae3f666 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c @@ -0,0 +1,90 @@ +/*

• • Copyright (C) 2011 Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/timer.h> +#include <asm/io.h>

+static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE; +static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE; +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;

+static void lpc32xx_timer_clock(u32 bit, int enable) +{

• if (enable)

• setbits_le32(&clk->timclk_ctrl1, bit);
  

• else

• clrbits_le32(&clk->timclk_ctrl1, bit);
  

+}

+static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq) +{

• writel(TIMER_TCR_COUNTER_RESET, &timer->tcr);
• writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
• writel(0, &timer->tc);
• writel(0, &timer->pr);
• /* Count mode is every rising PCLK edge */
• writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr);
• /* Set prescale counter value */
• writel((get_periph_clk_rate() / freq) - 1, &timer->pr);

+}

+static void lpc32xx_timer_count(struct timer_regs *timer, int enable) +{

• if (enable)

• writel(TIMER_TCR_COUNTER_ENABLE,  &timer->tcr);
  

• else

• writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr);
  

+}

+int timer_init(void) +{

• lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1);
• lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ);
• lpc32xx_timer_count(timer0, 1);
• return 0;

+}

+ulong get_timer(ulong base) +{

• return readl(&timer0->tc) - base;

+}

+void __udelay(unsigned long usec) +{

• lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1);
• lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000);
• lpc32xx_timer_count(timer1, 1);
• while (readl(&timer1->tc) < usec)

• /* NOP */;
  

• lpc32xx_timer_count(timer1, 0);
• lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0);

+}

+ulong get_tbclk(void) +{

• return CONFIG_SYS_HZ;

+} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h new file mode 100644 index 0000000..c1dad0a --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -0,0 +1,170 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_CLK_H +#define _LPC32XX_CLK_H

+#include <asm/types.h>

+#define OSC_CLK_FREQUENCY 13000000 +#define RTC_CLK_FREQUENCY 32768

+/* Clocking and Power Control Registers */ +struct clk_pm_regs {

• u32 reserved0[5];
• u32 boot_map; /* Boot Map Control Register */
• u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */
• u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
• /* Internal Start Signal Sources Registers */
• u32 start_er_int; /* Start Enable Register */
• u32 start_rsr_int; /* Start Raw Status Register */
• u32 start_sr_int; /* Start Status Register */
• u32 start_apr_int; /* Start Activation Polarity Register */
• /* Device Pin Start Signal Sources Registers */
• u32 start_er_pin; /* Start Enable Register */
• u32 start_rsr_pin; /* Start Raw Status Register */
• u32 start_sr_pin; /* Start Status Register */
• u32 start_apr_pin; /* Start Activation Polarity Register */
• /* Clock Control Registers */
• u32 hclkdiv_ctrl; /* HCLK Divider Control Register */
• u32 pwr_ctrl; /* Power Control Register */
• u32 pll397_ctrl; /* PLL397 Control Register */
• u32 osc_ctrl; /* Main Oscillator Control Register */
• u32 sysclk_ctrl; /* SYSCLK Control Register */
• u32 lcdclk_ctrl; /* LCD Clock Control Register */
• u32 hclkpll_ctrl; /* HCLK PLL Control Register */
• u32 reserved1;
• u32 adclk_ctrl1; /* ADC Clock Control1 Register */
• u32 usb_ctrl; /* USB Control Register */
• u32 sdramclk_ctrl; /* SDRAM Clock Control Register */
• u32 ddr_lap_nom; /* DDR Calibration Nominal Value */
• u32 ddr_lap_count; /* DDR Calibration Measured Value */
• u32 ddr_cal_delay; /* DDR Calibration Delay Value */
• u32 ssp_ctrl; /* SSP Control Register */
• u32 i2s_ctrl; /* I2S Clock Control Register */
• u32 ms_ctrl; /* Memory Card Control Register */
• u32 reserved2[3];
• u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */
• u32 reserved3[4];
• u32 test_clk; /* Test Clock Selection Register */
• u32 sw_int; /* Software Interrupt Register */
• u32 i2cclk_ctrl; /* I2C Clock Control Register */
• u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */
• u32 adclk_ctrl; /* ADC Clock Control Register */
• u32 pwmclk_ctrl; /* PWM Clock Control Register */
• u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */
• u32 timclk_ctrl1; /* Motor and Timer Clock Control */
• u32 spi_ctrl; /* SPI Control Register */
• u32 flashclk_ctrl; /* NAND Flash Clock Control Register */
• u32 reserved4;
• u32 u3clk; /* UART 3 Clock Control Register */
• u32 u4clk; /* UART 4 Clock Control Register */
• u32 u5clk; /* UART 5 Clock Control Register */
• u32 u6clk; /* UART 6 Clock Control Register */
• u32 irdaclk; /* IrDA Clock Control Register */
• u32 uartclk_ctrl; /* UART Clock Control Register */
• u32 dmaclk_ctrl; /* DMA Clock Control Register */
• u32 autoclk_ctrl; /* Autoclock Control Register */

+};

+/* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_HALF (0x2 << 7) +#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) +#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) +#define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) +#define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) +#define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) +#define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) +#define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) +#define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0)

+/* Power Control Register bits */ +#define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) +#define CLK_PWR_EMC_SREFREQ (1 << 9) +#define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) +#define CLK_PWR_SDRAM_SREFREQ (1 << 7) +#define CLK_PWR_HIGHCORE_LEVEL (1 << 5) +#define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) +#define CLK_PWR_SYSCLKEN_CTRL (1 << 3) +#define CLK_PWR_NORMAL_RUN (1 << 2) +#define CLK_PWR_HIGHCORE_CTRL (1 << 1) +#define CLK_PWR_STOP_MODE (1 << 0)

+/* SYSCLK Control Register bits */ +#define CLK_SYSCLK_PLL397 (1 << 1) +#define CLK_SYSCLK_MUX (1 << 0)

+/* HCLK PLL Control Register bits */ +#define CLK_HCLK_PLL_OPERATING (1 << 16) +#define CLK_HCLK_PLL_BYPASS (1 << 15) +#define CLK_HCLK_PLL_DIRECT (1 << 14) +#define CLK_HCLK_PLL_FEEDBACK (1 << 13) +#define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) +#define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) +#define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) +#define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) +#define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) +#define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) +#define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) +#define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) +#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) +#define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) +#define CLK_HCLK_PLL_LOCKED (1 << 0)

+/* Ethernet MAC Clock Control Register bits */ +#define CLK_MAC_RMII (0x3 << 3) +#define CLK_MAC_MII (0x1 << 3) +#define CLK_MAC_MASTER (1 << 2) +#define CLK_MAC_SLAVE (1 << 1) +#define CLK_MAC_REG (1 << 0)

+/* Timer Clock Control1 Register bits */ +#define CLK_TIMCLK_MOTOR (1 << 6) +#define CLK_TIMCLK_TIMER3 (1 << 5) +#define CLK_TIMCLK_TIMER2 (1 << 4) +#define CLK_TIMCLK_TIMER1 (1 << 3) +#define CLK_TIMCLK_TIMER0 (1 << 2) +#define CLK_TIMCLK_TIMER5 (1 << 1) +#define CLK_TIMCLK_TIMER4 (1 << 0)

+/* Timer Clock Control Register bits */ +#define CLK_TIMCLK_HSTIMER (1 << 1) +#define CLK_TIMCLK_WATCHDOG (1 << 0)

+/* UART Clock Control Register bits */ +#define CLK_UART(n) (1 << ((n) - 3))

+/* UARTn Clock Select Registers bits */ +#define CLK_UART_HCLK (1 << 16) +#define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) +#define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0)

+/* DMA Clock Control Register bits */ +#define CLK_DMA_ENABLE (1 << 0)

+unsigned int get_sys_clk_rate(void); +unsigned int get_hclk_pll_rate(void); +unsigned int get_hclk_clk_div(void); +unsigned int get_hclk_clk_rate(void); +unsigned int get_periph_clk_div(void); +unsigned int get_periph_clk_rate(void);

+#endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h new file mode 100644 index 0000000..41fcd32 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -0,0 +1,76 @@ +/*

• • Common definitions for LPC32XX board configurations
• • Copyright (C) 2011 Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_CONFIG_H +#define _LPC32XX_CONFIG_H

+/* Basic CPU architecture */ +#define CONFIG_ARM926EJS +#define CONFIG_ARCH_CPU_INIT

+#define CONFIG_NR_DRAM_BANKS_MAX 2

+/* 1KHz clock tick */ +#define CONFIG_SYS_HZ 1000

+/* UART configuration */ +#if (CONFIG_SYS_LPC32XX_UART >= 3) && (CONFIG_SYS_LPC32XX_UART <= 6) +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2) +#elif (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2)

||

\ + (CONFIG_SYS_LPC32XX_UART == 7) +#define CONFIG_LPC32XX_HSUART +#else +#error "define CONFIG_SYS_LPC32XX_UART in the range from 1 to 7" +#endif

+#if defined(CONFIG_SYS_NS16550_SERIAL) +#define CONFIG_SYS_NS16550

+#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK get_serial_clock()

+#define CONFIG_SYS_NS16550_COM1 UART3_BASE +#define CONFIG_SYS_NS16550_COM2 UART4_BASE +#define CONFIG_SYS_NS16550_COM3 UART5_BASE +#define CONFIG_SYS_NS16550_COM4 UART6_BASE +#endif

+#if defined(CONFIG_LPC32XX_HSUART) +#if CONFIG_SYS_LPC32XX_UART == 1 +#define HS_UART_BASE HS_UART1_BASE +#elif CONFIG_SYS_LPC32XX_UART == 2 +#define HS_UART_BASE HS_UART2_BASE +#else /* CONFIG_SYS_LPC32XX_UART == 7 */ +#define HS_UART_BASE HS_UART7_BASE +#endif +#endif

+#define CONFIG_SYS_BAUDRATE_TABLE \

• { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
  

+/* NOR Flash */ +#if defined(CONFIG_SYS_FLASH_CFI) +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_PROTECTION +#endif

+#endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h new file mode 100644 index 0000000..c5343c3 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -0,0 +1,64 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_CPU_H +#define _LPC32XX_CPU_H

+/* LPC32XX Memory map */

+/* AHB physical base addresses */ +#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base

*/

+#define SSP0_BASE 0x20084000 /* SSP0 registers base */ +#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */ +#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base

*/

+#define DMA_BASE 0x31000000 /* DMA controller registers base */ +#define USB_BASE 0x31020000 /* USB registers base */ +#define LCD_BASE 0x31040000 /* LCD registers base */ +#define ETHERNET_BASE 0x31060000 /* Ethernet registers base

*/

+#define EMC_BASE 0x31080000 /* EMC configuration registers base */

+/* FAB peripherals base addresses */ +#define CLK_PM_BASE 0x40004000 /* System control registers base */ +#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers

base */

+#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers

base */

+#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers

base */

+#define RTC_BASE 0x40024000 /* RTC registers base */ +#define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ +#define TIMER0_BASE 0x40044000 /* Timer0 registers base */ +#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ +#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base

*/

+/* APB peripherals base addresses */ +#define UART3_BASE 0x40080000 /* UART 3 registers base */ +#define UART4_BASE 0x40088000 /* UART 4 registers base */ +#define UART5_BASE 0x40090000 /* UART 5 registers base */ +#define UART6_BASE 0x40098000 /* UART 6 registers base */

+/* External SDRAM Memory Bank base addresses */ +#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address

*/

+#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address

*/

+/* External Static Memory Bank base addresses */ +#define EMC_CS0_BASE 0xE0000000 +#define EMC_CS1_BASE 0xE1000000 +#define EMC_CS2_BASE 0xE2000000 +#define EMC_CS3_BASE 0xE3000000

+#endif /* _LPC32XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h new file mode 100644 index 0000000..feb03bd --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/emc.h @@ -0,0 +1,92 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_EMC_H +#define _LPC32XX_EMC_H

+#include <asm/types.h>

+/* EMC Registers */ +struct emc_regs {

• u32 ctrl; /* Controls operation of the EMC */
• u32 status; /* Provides EMC status information */
• u32 config; /* Configures operation of the EMC */
• u32 reserved0[5];
• u32 control; /* Controls dyn memory operation */
• u32 refresh; /* Configures dyn memory refresh operation */
• u32 read_config; /* Configures the dyn memory read strategy */
• u32 reserved1;
• u32 t_rp; /* Precharge command period */
• u32 t_ras; /* Active to precharge command period */
• u32 t_srex; /* Self-refresh exit time */
• u32 reserved2[2];
• u32 t_wr; /* Write recovery time */
• u32 t_rc; /* Active to active command period */
• u32 t_rfc; /* Auto-refresh period */
• u32 t_xsr; /* Exit self-refresh to active command time */
• u32 t_rrd; /* Active bank A to active bank B latency */
• u32 t_mrd; /* Load mode register to active command time */
• u32 t_cdlr; /* Last data in to read command time */
• u32 reserved3[8];
• u32 extended_wait; /* time for static memory rd/wr transfers */
• u32 reserved4[31];
• u32 config0; /* Configuration information for the SDRAM */
• u32 rascas0; /* RAS and CAS latencies for the SDRAM */
• u32 reserved5[6];
• u32 config1; /* Configuration information for the SDRAM */
• u32 rascas1; /* RAS and CAS latencies for the SDRAM */
• u32 reserved6[54];
• struct emc_stat_t {

• u32 config;	/* Static memory configuration               */
  

• u32 waitwen;	/* Delay from chip select to write enable    */
  

• u32 waitoen;	/* Delay to output enable                    */
  

• u32 waitrd;	/* Delay to a read access                    */
  

• u32 waitpage;	/* Delay for async page mode read            */
  

• u32 waitwr;	/* Delay to a write access                   */
  

• u32 waitturn;	/* Number of bus turnaround cycles           */
  

• u32 reserved;
  

• } stat[4];
• u32 reserved7[96];
• struct emc_ahb_t {

• u32 control;	/* Control register for AHB                  */
  

• u32 status;	/* Status register for AHB                   */
  

• u32 timeout;	/* Timeout register for AHB                  */
  

• u32 reserved[5];
  

• } ahb[5];

+};

+/* Static Memory Configuration Register bits */ +#define EMC_STAT_CONFIG_WP (1 << 20) +#define EMC_STAT_CONFIG_EW (1 << 8) +#define EMC_STAT_CONFIG_PB (1 << 7) +#define EMC_STAT_CONFIG_PC (1 << 6) +#define EMC_STAT_CONFIG_PM (1 << 3) +#define EMC_STAT_CONFIG_32BIT (2 << 0) +#define EMC_STAT_CONFIG_16BIT (1 << 0) +#define EMC_STAT_CONFIG_8BIT (0 << 0)

+/* Static Memory Delay Registers */ +#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) +#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F) +#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) +#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) +#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)

+#endif /* _LPC32XX_EMC_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h new file mode 100644 index 0000000..b2cbfcd --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -0,0 +1,25 @@ +/*

• • Copyright (C) 2011 Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_SYS_PROTO_H +#define _LPC32XX_SYS_PROTO_H

+void lpc32xx_uart_init(unsigned int uart_id);

+#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h new file mode 100644 index 0000000..7d63763 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/timer.h @@ -0,0 +1,74 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_TIMER_H +#define _LPC32XX_TIMER_H

+#include <asm/types.h>

+/* Timer/Counter Registers */ +struct timer_regs {

• u32 ir; /* Interrupt Register */
• u32 tcr; /* Timer Control Register */
• u32 tc; /* Timer Counter */
• u32 pr; /* Prescale Register */
• u32 pc; /* Prescale Counter */
• u32 mcr; /* Match Control Register */
• u32 mr[4]; /* Match Registers */
• u32 ccr; /* Capture Control Register */
• u32 cr[4]; /* Capture Registers */
• u32 emr; /* External Match Register */
• u32 reserved[12];
• u32 ctcr; /* Count Control Register */

+};

+/* Timer/Counter Interrupt Register bits */ +#define TIMER_IR_CR(n) (1 << ((n) + 4)) +#define TIMER_IR_MR(n) (1 << (n))

+/* Timer/Counter Timer Control Register bits */ +#define TIMER_TCR_COUNTER_RESET (1 << 1) +#define TIMER_TCR_COUNTER_ENABLE (1 << 0) +#define TIMER_TCR_COUNTER_DISABLE (0 << 0)

+/* Timer/Counter Match Control Register bits */ +#define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) +#define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) +#define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n)))

+/* Timer/Counter Capture Control Register bits */ +#define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) +#define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) +#define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n)))

+/* Timer/Counter External Match Register bits */ +#define TIMER_EMR_EMC_TOGGLE(n) (0x3 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_CLEAR(n) (0x1 << (2 * (n) + 4)) +#define TIMER_EMR_EMC_NOTHING(n) (0x0 << (2 * (n) + 4)) +#define TIMER_EMR_EM(n) (1 << (n))

+/* Timer/Counter Count Control Register bits */ +#define TIMER_CTCR_INPUT(n) ((n) << 2) +#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) +#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) +#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) +#define TIMER_CTCR_MODE_TIMER (0x0 << 0)

+#endif /* _LPC32XX_TIMER_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h new file mode 100644 index 0000000..b613df8 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/uart.h @@ -0,0 +1,54 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_UART_H +#define _LPC32XX_UART_H

+#include <asm/types.h>

+/* UART Control Registers */ +struct uart_ctrl_regs {

• u32 ctrl; /* Control Register */
• u32 clkmode; /* Clock Mode Register */
• u32 loop; /* Loopback Control Register */

+};

+/* UART Control Register bits */ +#define UART_CTRL_UART3_MD_CTRL (1 << 11) +#define UART_CTRL_HDPX_INV (1 << 10) +#define UART_CTRL_HDPX_EN (1 << 9) +#define UART_CTRL_UART6_IRDA (1 << 5) +#define UART_CTRL_IR_TX6_INV (1 << 4) +#define UART_CTRL_IR_RX6_INV (1 << 3) +#define UART_CTRL_IR_RX_LENGTH (1 << 2) +#define UART_CTRL_IR_TX_LENGTH (1 << 1) +#define UART_CTRL_UART5_USB_MODE (1 << 0)

+/* UART Clock Mode Register bits */ +#define UART_CLKMODE_STATX(n) (1 << ((n) + 16)) +#define UART_CLKMODE_STAT (1 << 14) +#define UART_CLKMODE_MASK(n) (0x3 << (2 * (n) - 2)) +#define UART_CLKMODE_AUTO(n) (0x2 << (2 * (n) - 2)) +#define UART_CLKMODE_ON(n) (0x1 << (2 * (n) - 2)) +#define UART_CLKMODE_OFF(n) (0x0 << (2 * (n) - 2))

+/* UART Loopback Control Register bits */ +#define UART_LOOPBACK(n) (1 << ((n) - 1))

+#endif /* _LPC32XX_UART_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h new file mode 100644 index 0000000..133f29f --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h @@ -0,0 +1,51 @@ +/*

• • Copyright (C) 2011 by Vladimir Zapolskiy vz@mleia.com
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
• • MA 02110-1301, USA.
• */

+#ifndef _LPC32XX_WDT_H +#define _LPC32XX_WDT_H

+#include <asm/types.h>

+/* Watchdog Timer Registers */ +struct wdt_regs {

• u32 isr; /* Interrupt Status Register */
• u32 ctrl; /* Control Register */
• u32 counter; /* Counter Value Register */
• u32 mctrl; /* Match Control Register */
• u32 match0; /* Match 0 Register */
• u32 emr; /* External Match Control Register */
• u32 pulse; /* Reset Pulse Length Register */
• u32 res; /* Reset Source Register */

+};

+/* Watchdog Timer Control Register bits */ +#define WDTIM_CTRL_PAUSE_EN (1 << 2) +#define WDTIM_CTRL_RESET_COUNT (1 << 1) +#define WDTIM_CTRL_COUNT_ENAB (1 << 0)

+/* Watchdog Timer Match Control Register bits */ +#define WDTIM_MCTRL_RESFRC2 (1 << 6) +#define WDTIM_MCTRL_RESFRC1 (1 << 5) +#define WDTIM_MCTRL_M_RES2 (1 << 4) +#define WDTIM_MCTRL_M_RES1 (1 << 3) +#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2) +#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1) +#define WDTIM_MCTRL_MR0_INT (1 << 0)

+#endif /* _LPC32XX_WDT_H */