-----Original Message----- From: york sun Sent: Friday, August 26, 2016 11:01 PM To: Qianyu Gong qianyu.gong@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; Shaohui Xie shaohui.xie@nxp.com; Zhiqiang Hou zhiqiang.hou@nxp.com; Wenbin Song wenbin.song@nxp.com Subject: Re: [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
On 08/26/2016 04:40 AM, Gong Qianyu wrote:
From: Mingkai Hu mingkai.hu@nxp.com
Use 3 cycles.
Care to explain more here?
Hi York,
According to design, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, So increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues.
Thanks, Mingkai