From: Jens Gehrlein jens.gehrlein@tqs.de
This makes it necessary to prescale PITCLK by 512.
This patch is necessary for revision 102 and above of the TQM885D. Revisions 100 and 101 of the TQM885D will not work with this patch applied. But this should not be a problem, since there are only a few prototypes of this revisions floating around.
Signed-off-by: Jens Gehrlein jens.gehrlein@tqs.de Signed-off-by: Martin Krause martin.krause@tqs.de ---
cpu/mpc8xx/speed.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 101d5f9..4173092 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -93,11 +93,23 @@ unsigned long measure_gclk(void) ulong msr_val;
#ifdef CFG_8XX_XIN +#ifdef CONFIG_TQM885D + /* TQM885D uses the OSCM (MODCK[1:2]=00, SCCR[PTSEL]=0, SCCR[PTDIV]=0). + * The clock on the EXTAL input is 10 MHz (instead of 32768 Hz as + * on some other TQM8xx), so SCCR[PTDIV] must be set to achieve a + * PITCLK prescaler of 512. + */ + ulong sccr_val; + sccr_val = immr->im_clkrst.car_sccr & ~SCCR_RTSEL; + sccr_val |= SCCR_RTDIV; + immr->im_clkrst.car_sccr = sccr_val; +#else /* dont use OSCM, only use EXTCLK/512 */ immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; +#endif /* CONFIG_TQM885D */ #else immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV); -#endif +#endif /* CFG_8XX_XIN */
/* Reset + Stop Timer 2, no cascading */