12 Oct
2009
12 Oct
'09
8:31 a.m.
Hi Kumar,
I have tried using "fsl_ddr_set_memctl_regs()". But this can't get fit into 4K NAND_SPL Loader.
Regards, Dipen
On Oct 9, 2009, at 12:42 PM, Dipen Dudhat wrote:
+void initsdram(void) +{
- volatile ccsr_ddr_t *ddr= (ccsr_ddr_t
*)CONFIG_SYS_MPC85xx_DDR_ADDR;
- int d_init, dbw;
- volatile ccsr_gpio_t *pgpio = (void *)
(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- unsigned int ddr_size;
- sys_info_t sysinfo;
- phys_size_t dram_size = 0;
- set_next_law(0,LAW_SIZE_1G , LAW_TRGT_IF_DDR_1);
- out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
- out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
- out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2);
- out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
- out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
- out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
- out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
- out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
- out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
- out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
- out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
- out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
- out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
did fsl_ddr_set_memctl_regs() not work?
This function will take more space as we have only 4K space here. And this function contains 'printf' statements which is not valid.
So I think this is the simplest approach, as fsl_ddr_set_memctl_regs()
is doing the same thing. What do you suggest??
We can dummy out the printf. I'd prefer if we can try and use it. It unifies the register setting in one place which is key.
- k