On 07/05/2016 01:13 AM, Gong Qianyu wrote:
From: Mingkai Hu mingkai.hu@nxp.com
The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Signed-off-by: Mihai Bantea mihai.bantea@freescale.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com
v3:
- No change.
v2:
- Move serdes 2 support to a new patch.
- Fix SVR and add LS1026A SVR.
- Add SoC descriptions in README.soc.
- Remove ls1046a errata.
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 42 +++++++++ .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 25 +++++- arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 99 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 27 ++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 + .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 + 8 files changed, 200 insertions(+), 3 deletions(-)
Applied to fsl-qoriq master. Awaiting upstream. Thanks.
York