From: Roy Zang tie-fei.zang@freescale.com
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command.
Signed-off-by: Roy Zang tie-fei.zang@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 22 ++++++++++++++++++++++ drivers/usb/host/ehci-fsl.c | 21 --------------------- 2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index de9d916..8b12dd2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -623,6 +623,28 @@ skip_l2: } #endif
+#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) + ccsr_usb_phy_t *usb_phy = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI | + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); + setbits_be32(&usb_phy->port1.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port1.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port1.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); + setbits_be32(&usb_phy->port2.ctrl, + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); + setbits_be32(&usb_phy->port2.drvvbuscfg, + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); + setbits_be32(&usb_phy->port2.pwrfltcfg, + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 81a70c0..f54b408 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -89,27 +89,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
if (!strcmp(phy_type, "utmi")) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) -#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) - ccsr_usb_phy_t *usb_phy = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; - setbits_be32(&usb_phy->pllprg[1], - CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | - CONFIG_SYS_FSL_USB_PLLPRG2_MFI | - CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); - setbits_be32(&usb_phy->port1.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); - setbits_be32(&usb_phy->port1.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); - setbits_be32(&usb_phy->port1.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); - setbits_be32(&usb_phy->port2.ctrl, - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); - setbits_be32(&usb_phy->port2.drvvbuscfg, - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); - setbits_be32(&usb_phy->port2.pwrfltcfg, - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); -#endif setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); setbits_be32(&ehci->control, UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */