Hi Chris,
On Wed, Feb 26 2020, Chris Packham wrote:
From: Chris Packham chris.packham@alliedtelesis.co.nz
Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG)
Have you seen memory access reliability problems because of this issue?
The code is based on changes from Marvell's U-Boot, specifically:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd27040... https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8... https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2... https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2...
The last link looks duplicated.
baruch