13 Aug
2015
13 Aug
'15
3:19 p.m.
On Fri, Jul 24, 2015 at 09:22:11AM +0200, Alexander Stein wrote:
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes.
Signed-off-by: Alexander Stein alexanders83@web.de Acked-by: Stephen Warren swarren@wwwdotorg.org Tested-by: Stephen Warren swarren@wwwdotorg.org
Applied to u-boot/master, thanks!
--
Tom