On 06/02/2016 01:56 PM, Pavel Machek wrote:
This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.
Signed-off-by: Pavel Machek pavel@denx.de
v2: add diffstat
arch/arm/dts/Makefile | 1 arch/arm/dts/socfpga_cyclone5_is1.dts | 109 +++++ arch/arm/mach-socfpga/Kconfig | 6 board/is1/MAINTAINERS | 6 board/is1/Makefile | 5 board/is1/qts/iocsr_config.h | 660 ++++++++++++++++++++++++++++++++++ board/is1/qts/pinmux_config.h | 219 +++++++++++ board/is1/qts/pll_config.h | 85 ++++ board/is1/qts/sdram_config.h | 341 +++++++++++++++++ configs/socfpga_is1_defconfig | 43 ++ include/configs/socfpga_is1.h | 83 ++++ 11 files changed, 1558 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 92c7545..a397c69 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \
- socfpga_cyclone5_is1.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_de0_nano_soc.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts new file mode 100644 index 0000000..cdd2c99 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -0,0 +1,109 @@ +/*
- Copyright (C) 2012 Altera Corporation <www.altera.com>
This copyright notice needs to be updated.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include "socfpga_cyclone5.dtsi"
+/ {
- model = "Altera SOCFPGA IS1 board";
- compatible = "altr,socfpga-cyclone5", "altr,socfpga";
The compatible string needs at least one vendor-specific entry.
- chosen {
bootargs = "console=ttyS0,115200";- };
- memory {
name = "memory";device_type = "memory";reg = <0x0 0x10000000>;- };
- aliases {
/* this allow the ethaddr uboot environment variable contents* to be added to the gmac1 device tree blob.*/
Please just drop this comment or fix the formatting of multiline comment.
ethernet0 = &gmac1;udc0 = &usb1;- };
- regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";regulator-name = "3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;- };
- soc {
u-boot,dm-pre-reloc;- };
+};
[...]
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h new file mode 100644 index 0000000..77c3193 --- /dev/null +++ b/include/configs/socfpga_is1.h @@ -0,0 +1,83 @@ +/*
- Copyright (C) 2014 Marek Vasut marex@denx.de
This copyright notice needs to be updated.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_SOCFPGA_IS1_H__ +#define __CONFIG_SOCFPGA_IS1_H__
+#include <asm/arch/base_addr_ac5.h>
+/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG
+/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x10000000
+/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "zImage" +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTCOMMAND "run qspiload" +#define CONFIG_LOADADDR 0x01000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS +#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
These two are controlled by OF and not needed here.
+#define PHY_ANEG_TIMEOUT 8000 +#define CONFIG_ARP_TIMEOUT 500UL
+/* PHY */ +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 +#endif
+/*
- enable UBIFS support, it's required to load the FPGA netlist
- and/or other boot files (kernel, device tree) from QSPI flash
- when these files do not reside in their individual partitions
- */
+#define CONFIG_RBTREE +#define CONFIG_LZO
I believe these two are already defined in socfpga_common.h
+/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \
- "verify=n\0" \
- "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
This loadaddr is set by CONFIG_LOADADDR (above)
- "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \- "bootimage=zImage\0" \
- "fdt_addr=100\0" \
- "fdtimage=socfpga.dtb\0" \
- "bootm ${loadaddr} - ${fdt_addr}\0" \
- "mmcroot=/dev/mmcblk0p2\0" \
- "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${mmcroot} rw rootwait;" \"bootz ${loadaddr} - ${fdt_addr}\0" \- "mmcload=mmc rescan;" \
"load mmc 0:1 ${loadaddr} ${bootimage};" \"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \- "qspiload=sf probe && mtdparts default && run ubiload\0" \
- "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
" root=${qspiroot} rw rootfstype=${qspirootfstype};"\"bootm ${loadaddr} - ${fdt_addr}\0" \- "uboot_env_complete=yes\0"
Can we drop this extra environment? It looks like a copy of the CV SoCDK env, which is broken nonetheless, so unless it's used, drop it in V3 please.
+/*
- Bootcounter
- */
+#define CONFIG_BOOTCOUNT_LIMIT +/* last 2 lwords in OCRAM */ +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 +#define CONFIG_SYS_BOOTCOUNT_BE
+/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h>
+#endif /* __CONFIG_SOCFPGA_IS1_H__ */