Hi Pratyush,
On Thu, 17 Dec 2020 at 08:19, Pratyush Yadav p.yadav@ti.com wrote:
[Dropping Jean-Jacques Hiblot because his email will bounce anyway.]
Hi Simon,
On 16/12/20 08:25AM, Simon Glass wrote:
Most drivers use these access methods but a few do not. Update them.
In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check.
Your series does not apply cleanly on the tip of u-boot master (a439136599 as of writing this). Is this dependent on some other series or branch?
It's actually on top of -next
But see u-boot-dm/acc-working for the tree.
Signed-off-by: Simon Glass sjg@chromium.org
[...]
diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index b9868505a3b..00e0282dcc0 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -12,6 +12,7 @@ #include <regmap.h> #include <syscon.h> #include <dm/device.h> +#include <dm/device-internal.h> #include <dm/device_compat.h> #include <dm/read.h> #include <dm/devres.h> @@ -68,7 +69,7 @@ static int mmio_mux_probe(struct udevice *dev) fields = devm_kmalloc(dev, num_fields * sizeof(*fields), __GFP_ZERO); if (!fields) return -ENOMEM;
dev->priv = fields;
dev_set_priv(dev, fields);Ok.
mux_reg_masks = devm_kmalloc(dev, num_fields * 2 * sizeof(u32), __GFP_ZERO);[...]
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index b746501f5ff..67980431ba0 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -27,7 +27,7 @@
static int cadence_spi_write_speed(struct udevice *bus, uint hz) {
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus);I am confused. Grepping on the current tip of master (a439136599), I see no hits for dev_get_plat(). Your series does not introduce it either. Patch 18/18 changes it but I don't see it being added anywhere. What am I missing?
The dev_get_platdata() was renamed in a previous series to dev_get_plat().
struct cadence_spi_priv *priv = dev_get_priv(bus); cadence_qspi_apb_config_baudrate_div(priv->regbase,@@ -130,7 +130,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
static int cadence_spi_set_speed(struct udevice *bus, uint hz) {
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus); struct cadence_spi_priv *priv = dev_get_priv(bus); int err;@@ -165,7 +165,7 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
static int cadence_spi_probe(struct udevice *bus) {
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus); struct cadence_spi_priv *priv = dev_get_priv(bus); struct clk clk; int ret;@@ -212,7 +212,7 @@ static int cadence_spi_remove(struct udevice *dev)
static int cadence_spi_set_mode(struct udevice *bus, uint mode) {
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus); struct cadence_spi_priv *priv = dev_get_priv(bus); /* Disable QSPI */@@ -235,7 +235,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, const struct spi_mem_op *op) { struct udevice *bus = spi->dev->parent;
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus); struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; int err = 0;@@ -284,7 +284,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
static int cadence_spi_of_to_plat(struct udevice *bus) {
struct cadence_spi_plat *plat = bus->plat;
struct cadence_spi_plat *plat = dev_get_plat(bus); ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0);Anyway, assuming dev_get_plat() looks like:
void *dev_get_plat(const struct udevice *dev) { return dev->plat; }
Acked-by: Pratyush Yadav p.yadav@ti.com
for drivers/{mux/mmio.c,spi/cadence_qspi.c}.
Thanks for looking at this.
Regards, Simon