From: Dinesh Maniyam dinesh.maniyam@intel.com
The patch is to poll for thread complete status to ensure the descriptor processing is complete. If complete then can ensure controller already update the descriptor status.
Signed-off-by: Dinesh Maniyam dinesh.maniyam@intel.com --- drivers/mtd/nand/raw/cadence_nand.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c index 429a5e8017..33e8b79520 100644 --- a/drivers/mtd/nand/raw/cadence_nand.c +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -514,6 +514,7 @@ cadence_nand_cdma_send_and_wait(struct cadence_nand_info *cadence, { struct cadence_nand_irq_status irq_mask, irq_status = {0}; int status; + u32 val;
irq_mask.trd_status = BIT(thread); irq_mask.trd_error = BIT(thread); @@ -525,6 +526,14 @@ cadence_nand_cdma_send_and_wait(struct cadence_nand_info *cadence, if (status) return status;
+ /* Make sure the descriptor processing is complete */ + status = readl_poll_timeout(cadence->reg + TRD_COMP_INT_STATUS, val, + (val & BIT(thread)), TIMEOUT_US); + if (status) { + pr_err("cmd thread completion timeout!\n"); + return status; + } + cadence_nand_wait_for_irq(cadence, &irq_mask, &irq_status);
if (irq_status.status == 0 && irq_status.trd_status == 0 &&