Subject: Re: 回复: 回复: [EXT] Re: [PATCH v3 03/17] pinctrl: nxp: add SCMI pin control protocol driver
On 1/7/25 7:39 AM, Alice Guo (OSS) wrote:
-----邮件原件----- 发件人: Marek Vasut marex@denx.de 发送时间: 2025年1月7日 4:46 收件人: Alice Guo (OSS) alice.guo@oss.nxp.com; Tom Rini trini@konsulko.com; Stefano Babic sbabic@denx.de; Fabio
Estevam
festevam@gmail.com; dl-uboot-imx uboot-imx@nxp.com;
Lukasz
Majewski lukma@denx.de; Sean Anderson
seanga2@gmail.com; Simon
Glass sjg@chromium.org; Alper Nebi Yasak
抄送: u-boot@lists.denx.de; tharvey@gateworks.com; Peng Fan peng.fan@nxp.com; Ranjani Vaidyanathan ranjani.vaidyanathan@nxp.com; Ye Li ye.li@nxp.com 主题: Re: 回复: [EXT] Re: [PATCH v3 03/17] pinctrl: nxp: add SCMI
pin
control protocol driver
On 1/6/25 10:56 AM, Alice Guo (OSS) wrote:
This patch provides a driver for the SCMI pin control protocol which is based on ARM's System Control and Management
Interface (SCMI) 3.2.
Currently, only the PINCTRL_CONFIG_SET command is
implemented.
What is the SCMI provider for this platform ?
Hi Marek,
System Manager which runs on M core sets pin or group
configurations.
U-Boot sends a SCMI message to System Manager to perform
hardware
operations. You can refer to the source code for details:
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F github.com%2Fnxp-imx%2Fimx- sm&data=05%7C02%7Cpeng.fan%40nxp.com%7Cce165372497b40c20 3b408dd2f0df2fc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C 0%7C638718459160955158%7CUnknown%7CTWFpbGZsb3d8eyJFbXB 0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoi TWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=LMKHHdAJpBC iaHbrVIw1fg9Y%2FbqC7mWOUDfan00gItw%3D&reserved=0.
Can I use optee-os as a SCMI provider instead ?
You cannot replace System Manager with optee-os.
I think optee-os is also capable of being SCMI provider, so I have to wonder, why does NXP use custom hand-written SCMI provider instead of something already available, like that optee-os ?
System controller is the central controller of the system, and i.MX95 needs support safety.
We need to make sure when A55 crashes, safety core still work properly.
And one more question, would it be possible to make U-Boot NOT depend on SCMI at all and instead have regular clock/pinctrl drivers which can configure the hardware using plain register writes, like it is done on MX8M and older SoCs ?
See https://www.nxp.com/docs/en/data-sheet/IMX95CEC.pdf Only one boot mode: Low Power Boot (LPB): only M33 core is running after POR
You may configure TRDC to assign resources to A55, but you still need to make sure M33 work proper.
Regards, Peng.
That would surely make hardware
bring up easier .