The patch fixes endianness of SCFG_SPARECR8 register
Signed-off-by: Biwen Li biwen.li@nxp.com --- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index bb169aaaf4..00b6ad48ce 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -72,7 +72,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * returns zero, so its value is saved to a scrachpad register to be * read, that is why we don't read it from register ippdexpcr1 itself. */ - ippdexpcr1 = in_le32(&scfg->sparecr[7]); + ippdexpcr1 = in_be32(&scfg->sparecr[7]); out_be32(&rcpm->ippdexpcr1, ippdexpcr1);
if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC)