On Friday, August 22, 2014 at 05:02:37 AM, Li Ye-B37916 wrote:
Hi Marek,
On 8/22/2014 1:18 AM, Marek Vasut wrote:
On Thursday, August 21, 2014 at 07:10:32 PM, Fabio Estevam wrote:
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is set in the last BD, which causes FEC transmission to fail.
As explained by Ye Li:
"The TDAR bit is set when the descriptors are all out from TX ring, but the descriptor properly is in transmitting not READY.
Again, I do not understand this sentence :-(
When transmitting data, FEC internal DMA reads the TX descriptor and move the data from the buffer pointed by TX descriptor to FEC internal FIFO. All TX descriptors are managed in a ring. We found the TDAR is cleared at DMA starting last descriptor of the ring, not at DMA having last descriptor finished. So this bit clears earlier than the READY bit of last descriptor. The delay is the time for the data sending of last descriptor.
These are two signals, and in Ic simulation, we found the TDAR always clear prior than the READY bit of last BD.
And this is the behavior of which version of the FEC IP, the "old" one or the one present in MX6slx ?
This is the behavior of current FEC IP on mx6sx. For old ones, we did not do simulation for them, but it seems the TDAR clear at the last TX descriptor finished.
Thanks for clarification. Fabio, can you please document this with a big comment in the code ?
Best regards, Marek Vasut