Re: [U-Boot] [PATCHv2 4/6] dm: cache: add the pl310 cache controller driver

On Tue, 12 Mar 2019 at 22:41, Dinh Nguyen dinguyen@kernel.org wrote:

Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files.

This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS.

Signed-off-by: Dinh Nguyen dinguyen@kernel.org

v2: split out patch and address comments from Simon Glass

drivers/cache/Kconfig | 9 +++++ drivers/cache/Makefile | 1 + drivers/cache/cache-l2x0.c | 75 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/cache/cache-l2x0.c

Reviewed-by: Simon Glass sjg@chromium.org

nits below

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 8b7c9c7f9f..24def7ac0f 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -13,4 +13,13 @@ config CACHE is usually located on the same chip. This uclass can be used for configuring settings that be found from a device tree file.

+config L2X0_CACHE

•   tristate "PL310 cache driver"
  

•   select CACHE
  

•   depends on ARM
  

•   help
  

•     This driver is for the PL310 cache controller commonly found on
  

•     ARMv7(32-bit) devices. The driver configures the cache settings
  

•     found in the device tree.
  

endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 2ba68060c1..9deb961d91 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -1,3 +1,4 @@

obj-$(CONFIG_CACHE) += cache-uclass.o obj-$(CONFIG_SANDBOX) += sandbox_cache.o +obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c new file mode 100644 index 0000000000..a23a66c4a8 --- /dev/null +++ b/drivers/cache/cache-l2x0.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2019 Intel Corporation <www.intel.com>
• */

+#include <common.h> +#include <command.h> +#include <dm.h>

+#include <asm/io.h> +#include <asm/pl310.h>

+static void l2c310_of_parse(struct udevice *dev)

l2c310_of_parse_and_init()

(to be more descriptive)

+{

•   u32 tag[3] = { 0, 0, 0 };
  

•   u32 saved_reg, prefetch;
  

•   struct pl310_regs *regs = (struct pl310_regs *)dev_read_addr(dev);
  

•   /* Disable the L2 Cache */
  

•   clrbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);
  

•   saved_reg = readl(&regs->pl310_aux_ctrl);
  

•   if (!dev_read_u32(dev, "prefetch-data", &prefetch)) {
  

•           if (prefetch)
  

•                   saved_reg |= L310_AUX_CTRL_DATA_PREFETCH_MASK;
  

•           else
  

•                   saved_reg &= ~L310_AUX_CTRL_DATA_PREFETCH_MASK;
  

•   }
  

•   if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
  

•           if (prefetch)
  

•                   saved_reg |= L310_AUX_CTRL_INST_PREFETCH_MASK;
  

•           else
  

•                   saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK;
  

•   }
  

•   saved_reg |= dev_read_bool(dev, "arm,shared-override");
  

•   writel(saved_reg, &regs->pl310_aux_ctrl);
  

•   saved_reg = readl(&regs->pl310_tag_latency_ctrl);
  

•   if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
  

•           saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
  

•                        L310_LATENCY_CTRL_WR(tag[1] - 1) |
  

•                        L310_LATENCY_CTRL_SETUP(tag[2] - 1);
  

•   writel(saved_reg, &regs->pl310_tag_latency_ctrl);
  

•   saved_reg = readl(&regs->pl310_data_latency_ctrl);
  

•   if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3))
  

•           saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |
  

•                        L310_LATENCY_CTRL_WR(tag[1] - 1) |
  

•                        L310_LATENCY_CTRL_SETUP(tag[2] - 1);
  

•   writel(saved_reg, &regs->pl310_data_latency_ctrl);
  

•   /* Enable the L2 cache */
  

•   setbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN);
  

+}

+static int l2x0_probe(struct udevice *dev) +{

•   l2c310_of_parse(dev);
  

blank line

•   return 0;
  

+}

+static const struct udevice_id l2x0_ids[] = {

•   { .compatible = "arm,pl310-cache" },
  

•   {}
  

+};

+U_BOOT_DRIVER(pl310_cache) = {

•   .name   = "pl310_cache",
  

•   .id     = UCLASS_CACHE,
  

•   .of_match = l2x0_ids,
  

•   .probe  = l2x0_probe,
  

•   .flags  = DM_FLAG_PRE_RELOC,
  

+};

2.20.0

Regards, Simon