17 Jun
2019
17 Jun
'19
9:49 a.m.
On Wed, Jun 12, 2019 at 10:07:11PM +0800, Bin Meng wrote:
On Wed, Jun 12, 2019 at 9:49 PM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
On Wed, Jun 12, 2019 at 04:23:37PM +0300, Andy Shevchenko wrote:
On Wed, Jun 12, 2019 at 04:18:25PM +0300, Andy Shevchenko wrote:
commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a Author: Simon Glass sjg@chromium.org Date: Thu Apr 25 21:59:06 2019 -0600
x86: Don't set up MTRRs in SPLPlease revert ASAP before release, thanks!
So it looks that MTRRs are not programmed for Intel Edison to enable cache?
Simon, would you please take a look? I suspect simply revert this will break the Chromebook SPL build?
Since there is no activity on this and release is coming, I would propose to revert for now.
--
With Best Regards,
Andy Shevchenko