
28 Apr
2023
28 Apr
'23
6:08 a.m.
From: Peng Fan peng.fan@nxp.com
The HW_CTRL_SEL should be cleared when configuring PLL to avoid potential glitch
Reviewed-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx9/clock.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index a5f95fbcb8a..38e4cbbcc37 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -206,6 +206,9 @@ int configure_intpll(enum ccm_clk_src pll, u32 freq) return -EPERM; }
+ /* Clear PLL HW CTRL SEL */ + setbits_le32(®->ctrl.reg_clr, PLL_CTRL_HW_CTRL_SEL); + /* Bypass the PLL to ref */ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set);
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2.40.0