Introduce a new define to seperate out the virtual address that PCI memory is at from the physical address. In most situations these are mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- board/freescale/mpc8536ds/tlb.c | 2 +- board/freescale/mpc8540ads/tlb.c | 8 ++++---- board/freescale/mpc8541cds/tlb.c | 8 ++++---- board/freescale/mpc8544ds/tlb.c | 6 +++--- board/freescale/mpc8548cds/tlb.c | 6 +++--- board/freescale/mpc8555cds/tlb.c | 8 ++++---- board/freescale/mpc8560ads/tlb.c | 8 ++++---- board/freescale/mpc8568mds/tlb.c | 2 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8572ds/tlb.c | 6 +++--- include/configs/MPC8536DS.h | 14 +++++++++----- include/configs/MPC8540ADS.h | 6 ++++-- include/configs/MPC8541CDS.h | 6 ++++-- include/configs/MPC8544DS.h | 17 ++++++++++++----- include/configs/MPC8548CDS.h | 11 ++++++++--- include/configs/MPC8555CDS.h | 6 ++++-- include/configs/MPC8560ADS.h | 6 ++++-- include/configs/MPC8568MDS.h | 7 +++++-- include/configs/MPC8572DS.h | 9 ++++++--- 19 files changed, 84 insertions(+), 54 deletions(-)
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index f4bab55..ec76d5c 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 205c06a..a9925d5 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index bf957c0..ae6812f 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index c7442b2..d99441b 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -52,21 +52,21 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1),
/* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
/* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b7af25d..2267ad7 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCI1/PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1),
@@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
/* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index bf957c0..ae6812f 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 205c06a..a9925d5 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1),
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 1077552..8470c87 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0x80000000 512M PCI1 MEM * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1),
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index ca6f407..a238f3b 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -227,7 +227,7 @@ void pci_init_board(void)
pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) { + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { debug(" uli1572 read to %x\n", temp32); in_be32((unsigned *)temp32); } diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index c8ded15..f0115f2 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -63,16 +63,16 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1),
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 0aa01e1..885fc72 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -361,32 +361,36 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 2f1f462..f1167c0 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -310,16 +310,18 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000
/* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index fdbeb42..0099d2c 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -343,15 +343,17 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 6a74956..a9e7a96 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -266,41 +266,48 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
+#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 1, tgtid 1, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2,tgtid 2, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 3, direct to uli, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BUS2 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
#if defined(CONFIG_PCI) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1b075ea..618cd51 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -367,18 +367,21 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2 +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 @@ -386,8 +389,9 @@ extern unsigned long get_clock_freq(void); #endif
#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 @@ -398,6 +402,7 @@ extern unsigned long get_clock_freq(void); /* * RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 52907d6..d0f38b3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -341,15 +341,17 @@ extern unsigned long get_clock_freq(void); * General PCI * Addresses are mapped 1-1. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
+#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index f5e4ac6..0c82611 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -302,16 +302,18 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000
/* RapidIO MMU */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BUS +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 6d2b6d3..187a2b1 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -324,20 +324,23 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
+#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b8d6a40..35734b2 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -382,24 +382,27 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */
/* controller 3, direct to uli, tgtid 3, Base address 8000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000