Hi,
In addition to my first patch, please consider accepting this patch too. It prevents needless switching on and off PLL bypass mode and it allow single stepping through the SPL.
Hi,
this is how the imx-bootlets does it though. It's likely that FSL wants the PLL0 to run from XTAL when doing power configuration?
M
This patch removes mx28_power_clock2xtal, because all this function does is switching to reset-defaults, at a moment only reset defaults are already active.
It removes mx28_power_clock2pll becasue it is incomplete and because mx28_mem_init_clock does the same thing a little later on and does it corectly.
Maybe clock2pll should be fixed then ?
M
Signed-off-by: Robert Delien (robert@delien.nl)
From: Marek Vasut [marek.vasut@gmail.com] Sent: 26 January 2012 19:32 To: Fabio Estevam Cc: Robert Deliën; u-boot@lists.denx.de Subject: Re: mx28 spl power cpu clock configuration
Hi Robert,
On 1/25/12, Marek Vasut marek.vasut@gmail.com wrote:
Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock gating - before disabling PLL bypass?
This seems reasonable. Fabio, can you comment?
Could you please post a patch with your proposed change so that we can test it?
Hi Fabio,
I bought a really crappy custom board a few days ago (some china-made crap) sporting mx287, but apparently I'm hitting similar issue you do here.
When I swap power_init and mem_init though, the board boots fine, othervise it hangs.
M