On the km8321 boards is CONFIG_SYS_DDRCDR not defined, which leads to the DDRCDR not being configured at startup and still containing the reset value.
The required settings for our km8321 hardware designs are different than the reset value and must be set with CONFIG_SYS_DDRCDR, that is used by mpc83xx's cpu_init_f function at early CPU initialization.
The important settings are the DDR2 internal voltage level and the half-strength "drivers".
In our case where the DRAM chips are soldered on board and the routing for these signals under control, half-strength is sufficient as a few measurements done in the lasts have shown. Since all the hardware qualification tests have been performed with half strength, the nominal strength settings are removed in favor of the default reset half strength settings.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com
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Changes in v2: - Squashed commit 9/17 and 10/17 together into a single commit
include/configs/km/km8321-common.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 058b0ab..b2e68e3 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -65,6 +65,12 @@ HRCWH_BIG_ENDIAN | \ HRCWH_LALE_NORMAL)
+#define CONFIG_SYS_DDRCDR (\ + DDRCDR_EN | \ + DDRCDR_PZ_MAXZ | \ + DDRCDR_NZ_MAXZ | \ + DDRCDR_M_ODR) + #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \