-----Original Message----- From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Monday, August 17, 2020 12:34 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Tom Rini trini@konsulko.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com; Chee, Tien Fong tien.fong.chee@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [PATCH v1 08/16] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services
This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
include/linux/intel-smc.h | 573 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 573 insertions(+) create mode 100644 include/linux/intel-smc.h
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h new file mode 100644 index 0000000000..fa7d1dff56 --- /dev/null +++ b/include/linux/intel-smc.h
Suggest to use intel-socfpga-smc.h
@@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2017-2018, Intel Corporation */
+#ifndef __INTEL_SMC_H +#define __INTEL_SMC_H
+#include <linux/arm-smccc.h> +#include <linux/bitops.h>
+/*
- This file defines the Secure Monitor Call (SMC) message protocol
+used for
- service layer driver in normal world (EL1) to communicate with
+secure
- monitor software in Secure Monitor Exception Level 3 (EL3).
- This file is shared with secure firmware (FW) which is out of kernel tree.
Should be "u-boot tree"?
- An ARM SMC instruction takes a function identifier and up to 6
+64-bit
- register values as arguments, and can return up to 4 64-bit register
- value. The operation of the secure monitor is determined by the
value -> values
+parameter
- values passed in through registers.
- EL1 and EL3 communicates pointer as physical address rather than the
- virtual address.
- */
+/*
- Functions specified by ARM SMC Calling convention:
- FAST call executes atomic operations, returns when the requested
+operation
- has completed.
- STD call starts a operation which can be preempted by a non-secure
- interrupt. The call can return before the requested operation has
- completed.
- a0..a7 is used as register names in the descriptions below, on arm32
- that translates to r0..r7 and on arm64 to w0..w7.
- */
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
- ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL,
ARM_SMCCC_SMC_64, \
- ARM_SMCCC_OWNER_SIP, (func_num))
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
- ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL,
ARM_SMCCC_SMC_64, \
- ARM_SMCCC_OWNER_SIP, (func_num))
+/*
- Return values in INTEL_SIP_SMC_* call
- INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
- Secure monitor software doesn't recognize the request.
- INTEL_SIP_SMC_STATUS_OK:
- FPGA configuration completed successfully,
- In case of FPGA configuration write operation, it means secure
+monitor
- software can accept the next chunk of FPGA configuration data.
- INTEL_SIP_SMC_STATUS_BUSY:
- In case of FPGA configuration write operation, it means secure
+monitor
- software is still processing previous data & can't accept the next
+chunk
- of data. Service driver needs to issue
- INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
- completed block(s).
- INTEL_SIP_SMC_STATUS_ERROR:
- There is error during the FPGA configuration process.
This error only for FPGA configuration?
[....]
Regards Ley Foon