*****************************************************************
U-Boot
1.1.4 (Dec 29 2006 - 18:31:04)
MPC8260 Reset Status: External Soft, External
Hard
MPC8260 Clock Configuration
-
Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq
100-300
- dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf
1
- vco_out 264000000, scc_clk 66000000,
brg_clk 66000000
- cpu_clk 198000000, cpm_clk
132000000, bus_clk 66000000
CPU: MPC8260 (HiP3 Rev 01, Mask C.2
6K23A) at 198 MHz
Board: EST PSI8260
DRAM: 64 MB
*********************************************************************
Using the visionICE
emulator, got the following exception:
!HALT! -
[msg90003] Target Stopped for unknown reason; PC =
0x00000200
Upon
debugging, it was found that the code stops running after a couple of
instructions
into ram in the
assembly code segment of "in_ram" in the "cpu/mpc8260/start.S" in
the
u-boot source
directory.
The snippet of code
is below:
in_ram:
/*
* Relocation Function,
r14 point to got2+0x8000
*
* Adjust got2 pointers, no
need to check for 0, this
code
* already puts a few
entries in the table.
*/
li
r0,__got2_entries@sectoff@l
la
r3,GOT(_GOT2_TABLE_)
lwz r11,GOT(_GOT2_TABLE_)
mtctr
r0
/* not updating correctly */
<--------------------- /* tried adding sync and isync
here */
sub
r11,r3,r11
addi
r3,r3,-4
<---------------------- /* tried adding sync and isync here
*/
1: lwzu
r0,4(r3)
add
r0,r0,r11
stw
r0,0(r3)
bdnz
1b
Since the "mtctr r0"
is not updating properly, isync instruction was given at the 2
places
mentioned above.
But, this redirects the Program Counter to exception 0x00000200, either
immediately after
isync instruction or after a executing a single instruction. Please
note that
the icache
is enabled.
Is it anything to do
with Instruction pipelining, or do I need to look into any specific
Core
register
configuration.
Kindly let me know
what is going wrong here.
Regards,
Raghuveer