Hi,
I'm working with an OMAP3503 processor with a NAND chip attached via the GPMC interface. The NAND chip required at least 4-bit ECC outside of the first block. Currently, I write the MLO and u-boot.img files from u-boot using 1-bit hardware ECC (i.e. nandecc hw) to NAND and boot the board. It seems like this ECC is not really appropriate for writing u-boot though---is this correct?
If I understand correctly, I have three options: 1. Write u-boot to NAND from linux using BCH-8 which SPL can now understand 2. Write u-boot to NAND using the on-die ECC for my NAND chip 3. Write u-boot to NAND from u-boot using BCH8 (nandecc hw bch8)....this is my preference but when I try, I just see errors when trying to load u-boot from nand.
Forgive my stupidity if this has been asked and answered a hundred times---I've been getting thoroughly confused with the changes to the ECC on OMAP3 in u-boot.
--Ash