Re: [U-Boot] [PATCH V5 31/31] imx: add i.MX8MQ EVK support

Hi Stefano, On Mon, Jan 22, 2018 at 01:13:17PM +0100, Stefano Babic wrote:

Hi Peng,

On 10/01/2018 06:20, Peng Fan wrote:

...

Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM.

The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.4(release):o8.0.0_1.3.0_8m-prc-20171211-6-g54fb0797-dirty NOTICE: BL31: Built : 07:17:16, Jan 8 2018 NOTICE: sip svc init

U-Boot 2018.01-00038-gbd426c08ea (Jan 10 2018 - 13:14:56 +0800)

CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Using default environment

In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> "

If I see the output here, I am expecting the setup forthe working peripherals. Without ethernet working, why do we activate FEC and set the PHY ?

I would suggest to start with the minimal (=that is, all that is working), adding later when peripherals will be successfully added and tested.

ok. I'll minimize the changes.

...

Signed-off-by: Peng Fan peng.fan@nxp.com Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Stefano Babic sbabic@denx.de

---

arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8mq-evk.dts | 424 +++++++++ arch/arm/include/asm/arch-mx8m/ddr.h | 9 + arch/arm/mach-imx/mx8m/Kconfig | 12 + board/freescale/mx8mq_evk/Kconfig | 12 + board/freescale/mx8mq_evk/Makefile | 12 + board/freescale/mx8mq_evk/README | 47 + board/freescale/mx8mq_evk/ddr/ddr_init.c | 246 +++++ board/freescale/mx8mq_evk/ddr/ddrphy_train.c | 1272 ++++++++++++++++++++++++++ board/freescale/mx8mq_evk/ddr/helper.c | 101 ++ board/freescale/mx8mq_evk/mx8mq_evk.c | 156 ++++ board/freescale/mx8mq_evk/spl.c | 230 +++++ configs/mx8mq_evk_defconfig | 27 + include/configs/mx8mq_evk.h | 269 ++++++ 14 files changed, 2819 insertions(+) create mode 100644 arch/arm/dts/fsl-imx8mq-evk.dts create mode 100644 board/freescale/mx8mq_evk/Kconfig create mode 100644 board/freescale/mx8mq_evk/Makefile create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 board/freescale/mx8mq_evk/ddr/ddr_init.c create mode 100644 board/freescale/mx8mq_evk/ddr/ddrphy_train.c create mode 100644 board/freescale/mx8mq_evk/ddr/helper.c create mode 100644 board/freescale/mx8mq_evk/mx8mq_evk.c create mode 100644 board/freescale/mx8mq_evk/spl.c create mode 100644 configs/mx8mq_evk_defconfig create mode 100644 include/configs/mx8mq_evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a895c70284..299107977f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -391,6 +391,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \

dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb

+dtb-$(CONFIG_ARCH_MX8M) += fsl-imx8mq-evk.dtb

dtb-$(CONFIG_RCAR_GEN3) += \ r8a7795-h3ulcb.dtb \ r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/fsl-imx8mq-evk.dts b/arch/arm/dts/fsl-imx8mq-evk.dts new file mode 100644 index 0000000000..f0aa3485e6 --- /dev/null +++ b/arch/arm/dts/fsl-imx8mq-evk.dts @@ -0,0 +1,424 @@ +/*

• • Copyright (C) 2016 Freescale Semiconductor, Inc.
• • Copyright 2017 NXP
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License
• • as published by the Free Software Foundation; either version 2
• • of the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• */

+/dts-v1/;

+/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x40000000 0x00020000;

+#include "fsl-imx8mq.dtsi"

+/ {

• model = "Freescale i.MX8MQ EVK";
• compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
• chosen {

• bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
  

• };
• regulators {

• compatible = "simple-bus";
  

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• reg_usdhc2_vmmc: usdhc2_vmmc {
  

• 	compatible = "regulator-fixed";
  

• 	regulator-name = "VSD_3V3";
  

• 	regulator-min-microvolt = <3300000>;
  

• 	regulator-max-microvolt = <3300000>;
  

• 	gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  

• 	enable-active-high;
  

• };
  

• };
• pwmleds {

• compatible = "pwm-leds";
  

• ledpwm2 {
  

• 	label = "PWM2";
  

• 	pwms = <&pwm2 0 50000>;
  

• 	max-brightness = <255>;
  

• };
  

• };

+};

+&iomuxc {

• pinctrl-names = "default";
• imx8mq-evk {

• pinctrl_fec1: fec1grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
  

• 		MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
  

• 		MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
  

• 		MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
  

• 		MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
  

• 		MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
  

• 		MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
  

• 		MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
  

• 		MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
  

• 		MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
  

• 		MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
  

• 		MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
  

• 		MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
  

• 		MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
  

• 		MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
  

• 	>;
  

• };
  

• pinctrl_i2c1: i2c1grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL	0x4000007f
  

• 		MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA	0x4000007f
  

• 	>;
  

• };
  

• pinctrl_i2c2: i2c2grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x4000007f
  

• 		MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x4000007f
  

• 	>;
  

• };
  

• pinctrl_pwm2: pwm2grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
  

• 	>;
  

• };
  

• pinctrl_qspi: qspigrp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
  

• 		MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
  

• 		MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
  

• 		MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
  

• 		MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
  

• 		MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
  

• 	>;
  

• };
  

• pinctrl_usdhc1: usdhc1grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83
  

• 		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc3
  

• 		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc3
  

• 		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83
  

• 		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
  

• 	>;
  

• };
  

• pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85
  

• 		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc5
  

• 		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc5
  

• 		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85
  

• 		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
  

• 	>;
  

• };
  

• pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87
  

• 		MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6	0xc7
  

• 		MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7	0xc7
  

• 		MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87
  

• 		MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1
  

• 	>;
  

• };
  

• pinctrl_usdhc2_gpio: usdhc2grpgpio {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
  

• 		MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
  

• 	>;
  

• };
  

• pinctrl_usdhc2: usdhc2grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
  

• 		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
  

• 		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
  

• 		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
  

• 		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
  

• 		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
  

• 		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
  

• 	>;
  

• };
  

• pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85
  

• 		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5
  

• 		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc5
  

• 		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc5
  

• 		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc5
  

• 		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc5
  

• 		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
  

• 	>;
  

• };
  

• pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x87
  

• 		MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7
  

• 		MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc7
  

• 		MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc7
  

• 		MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc7
  

• 		MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc7
  

• 		MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1
  

• 	>;
  

• };
  

• pinctrl_sai2: sai2grp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
  

• 		MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
  

• 		MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
  

• 		MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
  

• 		MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
  

• 	>;
  

• };
  

• pinctrl_wdog: wdoggrp {
  

• 	fsl,pins = <
  

• 		MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  

• 	>;
  

• };
  

• };

+};

+&fec1 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_fec1>;
• phy-mode = "rgmii-id";
• phy-handle = <&ethphy0>;
• fsl,magic-packet;
• status = "okay";
• mdio {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• ethphy0: ethernet-phy@0 {
  

• 	compatible = "ethernet-phy-ieee802.3-c22";
  

• 	reg = <0>;
  

• 	at803x,led-act-blind-workaround;
  

• 	at803x,eee-disabled;
  

• };
  

• };

+};

+&i2c1 {

• clock-frequency = <100000>;
• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_i2c1>;
• status = "okay";
• pmic: pfuze100@08 {

• compatible = "fsl,pfuze100";
  

• reg = <0x08>;
  

• regulators {
  

• 	sw1a_reg: sw1ab {
  

• 		regulator-min-microvolt = <300000>;
  

• 		regulator-max-microvolt = <1875000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	sw1c_reg: sw1c {
  

• 		regulator-min-microvolt = <300000>;
  

• 		regulator-max-microvolt = <1875000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	sw2_reg: sw2 {
  

• 		regulator-min-microvolt = <800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	sw3a_reg: sw3ab {
  

• 		regulator-min-microvolt = <400000>;
  

• 		regulator-max-microvolt = <1975000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	sw4_reg: sw4 {
  

• 		regulator-min-microvolt = <800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	swbst_reg: swbst {
  

• 		regulator-min-microvolt = <5000000>;
  

• 		regulator-max-microvolt = <5150000>;
  

• 	};
  

• 	snvs_reg: vsnvs {
  

• 		regulator-min-microvolt = <1000000>;
  

• 		regulator-max-microvolt = <3000000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	vref_reg: vrefddr {
  

• 		regulator-always-on;
  

• 	};
  

• 	vgen1_reg: vgen1 {
  

• 		regulator-min-microvolt = <800000>;
  

• 		regulator-max-microvolt = <1550000>;
  

• 	};
  

• 	vgen2_reg: vgen2 {
  

• 		regulator-min-microvolt = <800000>;
  

• 		regulator-max-microvolt = <1550000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	vgen3_reg: vgen3 {
  

• 		regulator-min-microvolt = <1800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	vgen4_reg: vgen4 {
  

• 		regulator-min-microvolt = <1800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	vgen5_reg: vgen5 {
  

• 		regulator-min-microvolt = <1800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 		regulator-always-on;
  

• 	};
  

• 	vgen6_reg: vgen6 {
  

• 		regulator-min-microvolt = <1800000>;
  

• 		regulator-max-microvolt = <3300000>;
  

• 	};
  

• };
  

• };

+};

+&i2c2 {

• clock-frequency = <100000>;
• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_i2c2>;
• status = "disabled";

+};

+&pwm2 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_pwm2>;
• status = "okay";

+};

+&lcdif {

• status = "okay";
• disp-dev = "mipi_dsi_northwest";
• display = <&display0>;
• display0: display@0 {

• bits-per-pixel = <24>;
  

• bus-width = <24>;
  

• display-timings {
  

• 	native-mode = <&timing0>;
  

• 	timing0: timing0 {
  

• 	clock-frequency = <9200000>;
  

• 	hactive = <480>;
  

• 	vactive = <272>;
  

• 	hfront-porch = <8>;
  

• 	hback-porch = <4>;
  

• 	hsync-len = <41>;
  

• 	vback-porch = <2>;
  

• 	vfront-porch = <4>;
  

• 	vsync-len = <10>;
  

• 	hsync-active = <0>;
  

• 	vsync-active = <0>;
  

• 	de-active = <1>;
  

• 	pixelclk-active = <0>;
  

• 	};
  

• };
  

• };

+};

+&qspi {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_qspi>;
• status = "okay";
• flash0: n25q256a@0 {

• reg = <0>;
  

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• compatible = "micron,n25q256a";
  

• spi-max-frequency = <29000000>;
  

• spi-nor,ddr-quad-read-dummy = <6>;
  

• };

+};

+&usdhc1 {

• pinctrl-names = "default", "state_100mhz", "state_200mhz";
• pinctrl-0 = <&pinctrl_usdhc1>;
• pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
• pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
• bus-width = <8>;
• non-removable;
• status = "okay";

+};

+&usdhc2 {

• pinctrl-names = "default", "state_100mhz", "state_200mhz";
• pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
• pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
• pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
• bus-width = <4>;
• cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
• vmmc-supply = <&reg_usdhc2_vmmc>;
• status = "okay";

+};

+&wdog1 {

• pinctrl-names = "default";
• pinctrl-0 = <&pinctrl_wdog>;
• fsl,ext-reset-output;
• status = "okay";

+}; diff --git a/arch/arm/include/asm/arch-mx8m/ddr.h b/arch/arm/include/asm/arch-mx8m/ddr.h index b37382eab0..11016c9278 100644 --- a/arch/arm/include/asm/arch-mx8m/ddr.h +++ b/arch/arm/include/asm/arch-mx8m/ddr.h @@ -353,4 +353,13 @@ enum msg_response { TRAIN_FAIL = 0xff, };

+enum fw_type {

• FW_1D_IMAGE,
• FW_2D_IMAGE,

+};

+void ddr_init(void); +void ddr_load_train_code(enum fw_type type); +void lpddr4_800M_cfg_phy(void); +void dram_pll_init(void); #endif diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig index 3a84c2f2b0..e3b57b7915 100644 --- a/arch/arm/mach-imx/mx8m/Kconfig +++ b/arch/arm/mach-imx/mx8m/Kconfig @@ -7,4 +7,16 @@ config MX8M config SYS_SOC default "mx8m"

+choice

• prompt "NXP i.MX8M board select"
• optional

+config TARGET_MX8MQ_EVK

• bool "mx8mq_evk"
• select MX8M

+endchoice

+source "board/freescale/mx8mq_evk/Kconfig"

endif diff --git a/board/freescale/mx8mq_evk/Kconfig b/board/freescale/mx8mq_evk/Kconfig new file mode 100644 index 0000000000..4e23002803 --- /dev/null +++ b/board/freescale/mx8mq_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX8MQ_EVK

+config SYS_BOARD

• default "mx8mq_evk"

+config SYS_VENDOR

• default "freescale"

+config SYS_CONFIG_NAME

• default "mx8mq_evk"

+endif diff --git a/board/freescale/mx8mq_evk/Makefile b/board/freescale/mx8mq_evk/Makefile new file mode 100644 index 0000000000..286396ee96 --- /dev/null +++ b/board/freescale/mx8mq_evk/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y += mx8mq_evk.o

+ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o +endif diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README new file mode 100644 index 0000000000..e214401a8a --- /dev/null +++ b/board/freescale/mx8mq_evk/README @@ -0,0 +1,47 @@ +U-Boot for the NXP i.MX8MQ EVK board

+Quick Start +==================== +- Build the ARM Trusted firmware binary +- Build U-Boot +- Get ddr fimware and tools +- Generate flash.bin using imx-mkimage +- Boot

+Get and Build the ARM Trusted firmware +==================== +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf +$ make PLAT=imx8mq bl31

+Build U-Boot +==================== +$ export ARCH=arm64 +$ export CROSS_COMPILE=aarch64-poky-linux- +$ make mx8mq_evk_defconfig +$ make

+Get the ddr firmware and tools +==================== +Note: Better to use NXP released yocto to get the firmware in case

•  there is new releases.
  

+https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin +imx-mkimage: https://source.codeaurora.org/external/imx/imx-mkimage/

I am just asking which is the plan here. This is a fork of U-Boot's mkimage tool. I did not see attempts to push changes to imximage mainline.

Any thoughts ? This means that it is not possible inside U-Boot to produce a U-Boot image, but we need an external tool that was *based* on U-Boot code....

There are many containers, for i.MX8MQ, there are two containers. For i.MX8QM, there are more and more containers. Also take secure boot into consideration, it is hard to extend the current mkimage.

For long run, I could look into the support in u-boot, but I could not commit.

...

+Generate flash.bin using imx-mkimage +==================== +Copy bl31.bin u-boot-nodtb.bin u-boot-spl.bin fsl-imx8mq-evk.dtb to

• imx-mkimage/iMX8M
  

+Copy lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin

• lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin to
  

• imx-mkimage/iMX8M
  

+If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M

+make SOC=iMX8M flash_hdmi_spl_uboot or make SOC=iMX8M flash_spl_uboot to +generate flash.bin.

+Burn the flash.bin to MicroSD card offset 33KB +$sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33

+Boot +==================== +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. diff --git a/board/freescale/mx8mq_evk/ddr/ddr_init.c b/board/freescale/mx8mq_evk/ddr/ddr_init.c new file mode 100644 index 0000000000..9ff4341bd9 --- /dev/null +++ b/board/freescale/mx8mq_evk/ddr/ddr_init.c @@ -0,0 +1,246 @@ +/*

• • Copyright 2017 NXP
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/sys_proto.h> +#include <linux/iopoll.h>

+struct imx8m_ddrc_regs *ddrc_regs = (struct imx8m_ddrc_regs *)DDRC_IPS_BASE_ADDR(0); +static struct gpc_reg *gpc_reg = (struct gpc_reg *)GPC_BASE_ADDR; +static struct src *src = (struct src *)SRC_BASE_ADDR;

+void lpddr4_800mhz_cfg_umctl2(void) +{

• writel(0x00000001, &ddrc_regs->dbg1);
• writel(0x00000001, &ddrc_regs->pwrctl);
• writel(0x83080020, &ddrc_regs->mstr);
• writel(0x006180e0, &ddrc_regs->rfshtmg);
• writel(0xc003061b, &ddrc_regs->init0);
• writel(0x009d0000, &ddrc_regs->init1);
• writel(0x0000fe05, &ddrc_regs->init2);
• writel(0x00d4002d, &ddrc_regs->init3);
• writel(0x00310008, &ddrc_regs->init4);
• writel(0x00040009, &ddrc_regs->init5);
• writel(0x0046004d, &ddrc_regs->init6);
• writel(0x0005004d, &ddrc_regs->init7);
• writel(0x00000979, &ddrc_regs->rankctl);
• writel(0x1a203522, &ddrc_regs->dramtmg0);

I guess we will not have any improvement here, at least for first version.

I'll give a try to improve the ddr controller part. For ddr phy part, it is impossible to do that, it was autogenerated by tool from synopsys.

Thanks, Peng