Simon,
On 18.04.2019, at 06:32, Simon Glass sjg@chromium.org wrote:
Hi Kever,
On Mon, 1 Apr 2019 at 02:21, Kever Yang kever.yang@rock-chips.com wrote:
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs.
So this means that TPL inits SDRAM? That seems strange to me...why have SPL at all, then? What is SPL supported to do on RK3399 platforms?
For TPL->SPL implementation on Rockchip, we generally rely on the BootROM to load the TPL stage (to SRAM) and the SPL stage (to the start of DRAM). The BootROM usually limits the size of the SPL stage, so we can’t use a full U-Boot already.
Even more constricting are the TPL size constraints (as this seems to have originally only been intended to be size-optimized DRAM init code) on some devices.
Hope this explains the situation, Philipp.