From: Tien Fong Chee tien.fong.chee@intel.com
These series of patches enable peripheral bitstream being programmed into FPGA to get the DDR up running. This's also called early IO release, because the peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR.
Once DDR is up running, core bitstream from MMC which contains user FPGA design would be loaded into DDR location. socfpga loadfs would be called to program core bitstream into FPGA and entering user mode.
Lastly, u-boot-dtb.img from MMC FAT partition would be loaded to DDR, and up running from there.
For this whole mechanism to work, the SDMMC flash layout would be designed as shown in below:
RAW partition: 1. spl_w_dtb-mkpimage.bin mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin
FAT partition contains: FPGA FIT image(fit_spl_fpga.itb) -------------------------------- Early IO release method is recommended for the sake of performance, improve up to 86% compare to full bitstream.
To generate FPGA FIT image for Early IO release, runs this command: tools/mkimage -E -p 400 -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb
Before running above command, ensure U-Boot source directory contains both peripheral bitstream(ghrd_10as066n2.periph.rbf) and core bitstream(ghrd_10as066n2.core.rbf_.
For details of describing structure and contents of the FIT image, please refer board/altera/arria10-socdk/fit_spl_fpga.its
Additonal note: --------------- There is performance penalty if the memory used for loading the bitstream is unalligned to ARCH_DMA_MINALIGN inside function "static int get_cluster()" in fs/fat/fat.c. Sometimes child functions would alter the memory location and causing unalligned to ARCH_DMA_MINALIGN. This only happend when reading a FAT file by offset.
To avoid performance penalty, core bitstream(fpga-2) contains large size should be at 1st then following by peripheral bitstream(fpga-1) as shown in fit_spl_fpga.its.
After that, enable the DEBUG in fs/fat/fat.c and ensure no print out "FAT: Misaligned buffer address (%p)" when loading core bitstream on SPL console. Print out when loading peripheral bitstream can be ignored because the size is too small.
If there is print out, please set an allign data position by running mkimage with optional -p xxx when generating FIT image.
U-Boot image ------------ 3. u-boot-dtb.img
For the testing purpose, these 3 series of patches are required to apply 1st before applying this series of patches. 1. [U-Boot] [PATCH v4] misc: fs_loader: Add support for initializing block device https://www.mail-archive.com/u-boot@lists.denx.de/msg314453.html Version 4 under review
2. [U-Boot] [PATCH v2 1/4] spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT https://www.mail-archive.com/u-boot@lists.denx.de/msg313259.html All series Reviewed-by: Tom Rini trini@konsulko.com Some patches of the series Reviewed-by: Simon Goldschmidt
3. [U-Boot] [PATCH v2 1/2] fs: fat: dynamically allocate memory for temporary buffer https://www.mail-archive.com/u-boot@lists.denx.de/msg314470.html Version 2 under review
This series is working on top of u-boot.git - http://git.denx.de/u-boot.git .
Tien Fong Chee (7): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK spl : socfpga: Implement fpga bitstream loading with socfpga loadfs ARM: socfpga: Synchronize the configuration for A10 SoCDK ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 + .../include/mach/fpga_manager_arria10.h | 39 +- arch/arm/mach-socfpga/spl_a10.c | 46 ++- board/altera/arria10-socdk/fit_spl_fpga.its | 31 ++ configs/socfpga_arria10_defconfig | 21 +- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 34 +- drivers/fpga/socfpga_arria10.c | 417 ++++++++++++++++++++- include/configs/socfpga_common.h | 4 +- 8 files changed, 584 insertions(+), 26 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its