Hi Fabio,
On 06/01/2014 14:14, Fabio Estevam wrote:
According to e9fd66defd (ARM: mx6: define CONFIG_ARM_ERRATA_742230), the CONFIG_ARM_ERRATA_742230 option should only be applied to multi-core variants, so restrict its usage for quad and dual-lite only.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
include/configs/mx6_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 514d634..0b8db85 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -17,7 +17,9 @@ #ifndef __MX6_COMMON_H #define __MX6_COMMON_H
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) #define CONFIG_ARM_ERRATA_742230 +#endif #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 #define CONFIG_BOARD_POSTCLK_INIT
In Kernel I cannot read that the errata is related to a multicore processor. Indeed, it is related to the Cortex-A9 version.
"This option enables the workaround for the 742230 Cortex-A9 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction between two write operations may not ensure the correct visibility ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of the two writes. "
The fix was merged in kernel since a lot of time, before having multicore processors for ARM. At least the commit message does not seem coherent with the explanations in kernel. Maybe has solo a upgraded core version as dual/quad ?
Best regards, Stefano