On 3 February 2015 at 01:18, Akshay Saraswat akshay.s@samsung.com wrote:
This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel.
Secondary core power down happens in following steps:
Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon.kim@samsung.com Signed-off-by: Akshay Saraswat akshay.s@samsung.com
Changes since v1: - Removed unnecessary macros. - Changed names of few macros for better understanding. - Added MPIDR bit assignment info comment in power_down_core.
arch/arm/cpu/armv7/exynos/exynos5_setup.h | 3 ++ arch/arm/cpu/armv7/exynos/lowlevel_init.c | 69 ++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 5 ++ arch/arm/include/asm/arch-exynos/system.h | 87 +++++++++++++++++++++++++++++++ 4 files changed, 164 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org