-----Original Message----- From: Shengzhou Liu Sent: Monday, August 29, 2016 6:53 PM To: Qianyu Gong qianyu.gong@nxp.com; u-boot@lists.denx.de; york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; Shaohui Xie shaohui.xie@nxp.com; Zhiqiang Hou zhiqiang.hou@nxp.com; Wenbin Song wenbin.song@nxp.com; Qianyu Gong qianyu.gong@nxp.com Subject: RE: [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a
-----Original Message----- From: Gong Qianyu [mailto:Qianyu.Gong@nxp.com] Sent: Friday, August 26, 2016 7:29 PM To: u-boot@lists.denx.de; york sun york.sun@nxp.com Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; Shaohui Xie shaohui.xie@nxp.com; Zhiqiang
Hou
zhiqiang.hou@nxp.com; Wenbin Song wenbin.song@nxp.com;
Shengzhou
Liu shengzhou.liu@nxp.com; Qianyu Gong qianyu.gong@nxp.com Subject: [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a
From: Shengzhou Liu Shengzhou.Liu@nxp.com
Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com
arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c7e374c..3250290 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -238,6 +238,11 @@ #define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#define CONFIG_SYS_FSL_ERRATUM_A009801 #define +CONFIG_SYS_FSL_ERRATUM_A009803 #define
CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
LS1046 also need to enable ERRATUM_A008511 in this patch.
Sure, will add the A008511 as what we have worked out.
Thanks, Mingkai