Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/clk/uniphier/Makefile | 1 + drivers/clk/uniphier/clk-uniphier-core.c | 30 ++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier-sys.c | 34 ++++++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 2 ++ 4 files changed, 67 insertions(+) create mode 100644 drivers/clk/uniphier/clk-uniphier-sys.c
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index ed623aa56f75..54c7e09bd606 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,2 +1,3 @@ obj-y += clk-uniphier-core.o +obj-y += clk-uniphier-sys.o obj-y += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index eed21b9a6871..722cd6b060c8 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -146,6 +146,36 @@ static int uniphier_clk_probe(struct udevice *dev) }
static const struct udevice_id uniphier_clk_match[] = { + /* System clock */ + { + .compatible = "socionext,uniphier-ld4-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pro4-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-sld8-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pro5-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs2-clock", + .data = (ulong)&uniphier_pxs2_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-ld11-clock", + .data = (ulong)&uniphier_ld20_sys_clk_data, + }, + { + .compatible = "socionext,uniphier-ld20-clock", + .data = (ulong)&uniphier_ld20_sys_clk_data, + }, + /* Media I/O clock */ { .compatible = "socionext,uniphier-ld4-mio-clock", .data = (ulong)&uniphier_mio_clk_data, diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c new file mode 100644 index 000000000000..709fa5081a42 --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016-2017 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "clk-uniphier.h" + +const struct uniphier_clk_gate_data uniphier_pxs2_sys_clk_gate[] = { + UNIPHIER_CLK_GATE(8, 0x2104, 10), /* stdmac */ + UNIPHIER_CLK_GATE(12, 0x2104, 6), /* gio (Pro4, Pro5) */ + UNIPHIER_CLK_GATE(14, 0x2104, 16), /* usb30 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE(15, 0x2104, 17), /* usb31 (Pro4, Pro5, PXs2) */ + UNIPHIER_CLK_GATE(16, 0x2104, 19), /* usb30-phy (PXs2) */ + UNIPHIER_CLK_GATE(20, 0x2104, 20), /* usb31-phy (PXs2) */ + UNIPHIER_CLK_END +}; + +const struct uniphier_clk_data uniphier_pxs2_sys_clk_data = { + .gate = uniphier_pxs2_sys_clk_gate, +}; + +const struct uniphier_clk_gate_data uniphier_ld20_sys_clk_gate[] = { + UNIPHIER_CLK_GATE(8, 0x210c, 8), /* stdmac */ + UNIPHIER_CLK_GATE(14, 0x210c, 14), /* usb30 (LD20) */ + UNIPHIER_CLK_GATE(16, 0x210c, 12), /* usb30-phy0 (LD20) */ + UNIPHIER_CLK_GATE(17, 0x210c, 13), /* usb30-phy1 (LD20) */ + UNIPHIER_CLK_END +}; + +const struct uniphier_clk_data uniphier_ld20_sys_clk_data = { + .gate = uniphier_ld20_sys_clk_gate, +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index f9a560ee73d3..770a3225e1a3 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -50,6 +50,8 @@ struct uniphier_clk_data { .rates = {(_reg),}, \ }
+extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data; +extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data; extern const struct uniphier_clk_data uniphier_mio_clk_data;
#endif /* __CLK_UNIPHIER_H__ */