On 03/22/2016 10:43 PM, Saksham Jain wrote:
This commit solves CAAM coherency issue on ls2080. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures. But even if any data in proximity of these structures is read by core, these structures again are fetched in caches.
To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable.
So, this commit makes CAAM transcations as Write Back with Write and Read Allocate.
Signed-off-by: Saksham Jain saksham.jain@nxp.com
Changes for v2:
- No changes
Changes for v3:
- No changes
Changes for v4:
- Cleaned up commit message
Changes for v5:
- Cleaned up commit message
drivers/crypto/fsl/jr.c | 13 +++++++++++++ drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+)
Minor change to commit message.
Applied to u-boot-fsl-qoriq master. Awaiting upstream.
Thanks.
York