CONFIG options must not use lower-case letter. Convert this to upper case.
Signed-off-by: Simon Glass sjg@chromium.org ---
(no changes since v1)
arch/m68k/Kconfig | 4 ++-- arch/m68k/Makefile | 4 ++-- arch/m68k/cpu/mcf5445x/cpu_init.c | 12 ++++++------ arch/m68k/cpu/mcf5445x/dspi.c | 4 ++-- arch/m68k/cpu/mcf5445x/speed.c | 4 ++-- arch/m68k/cpu/mcf5445x/start.S | 8 ++++---- arch/m68k/include/asm/cache.h | 4 ++-- arch/m68k/include/asm/global_data.h | 2 +- arch/m68k/include/asm/immap_5441x.h | 2 +- drivers/mmc/fsl_esdhc_imx.c | 12 ++++++------ 10 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 6781ba28c7a..4e2a9075b10 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -50,7 +50,7 @@ config MCF537x select DM_SERIAL bool
-config MCF5441x +config MCF5441X select OF_CONTROL select DM select DM_SERIAL @@ -108,7 +108,7 @@ config M5373
config M54418 bool - select MCF5441x + select MCF5441X
# peripherals config CF_DSPI diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index cf4562c55f1..b44726242d2 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -16,12 +16,12 @@ cpuflags-$(CONFIG_M5282) := -mcpu=5282 cpuflags-$(CONFIG_M5307) := -mcpu=5307 cpuflags-$(CONFIG_MCF5301X) := -mcpu=53015 -fPIC cpuflags-$(CONFIG_MCF532X) := -mcpu=5329 -fPIC -cpuflags-$(CONFIG_MCF5441x) := -mcpu=54418 -fPIC +cpuflags-$(CONFIG_MCF5441X) := -mcpu=54418 -fPIC
PLATFORM_CPPFLAGS += $(cpuflags-y)
-ldflags-$(CONFIG_MCF5441x) := --got=single +ldflags-$(CONFIG_MCF5441X) := --got=single
ifneq (,$(findstring -linux-,$(shell $(CC) --version))) ifneq (,$(findstring GOT,$(shell $(LD) --help))) diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 1ce244872f1..a70ecfbae73 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -73,7 +73,7 @@ void cfspi_port_conf(void) { gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X pm_t *pm = (pm_t *)MMAP_PM;
out_8(&gpio->par_dspi0, @@ -98,7 +98,7 @@ void cpu_init_f(void) { gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X scm_t *scm = (scm_t *) MMAP_SCM; pm_t *pm = (pm_t *) MMAP_PM;
@@ -203,7 +203,7 @@ void cpu_init_f(void) out_8(&gpio->par_sdhch, 0xff); out_8(&gpio->par_sdhcl, 0xff); #endif -#endif /* CONFIG_MCF5441x */ +#endif /* CONFIG_MCF5441X */
/* FlexBus Chipselect */ init_fbcs(); @@ -240,13 +240,13 @@ int cpu_init_r(void) void uart_port_conf(int port) { gpio_t *gpio = (gpio_t *) MMAP_GPIO; -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X pm_t *pm = (pm_t *) MMAP_PM; #endif
/* Setup Ports: */ switch (port) { -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X case 0: /* UART0 */ out_8(&pm->pmcr0, 24); @@ -340,7 +340,7 @@ int fecpin_setclear(fec_info_t *info, int setclear) if (fec_get_base_addr(0, &fec0_base)) return -1;
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X if (setclear) { out_8(&gpio->par_fec, 0x03); out_8(&gpio->srcr_fec, 0x0F); diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c index 456af171a4e..628be0c8bbb 100644 --- a/arch/m68k/cpu/mcf5445x/dspi.c +++ b/arch/m68k/cpu/mcf5445x/dspi.c @@ -15,7 +15,7 @@ void dspi_chip_select(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X switch (cs) { case 0: clrbits_8(&gpio->par_dspi0, @@ -37,7 +37,7 @@ void dspi_chip_unselect(int cs) { struct gpio *gpio = (struct gpio *)MMAP_GPIO;
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X if (cs == 1) clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1); #endif diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index eb73da68c6b..59a6625a4fd 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -63,7 +63,7 @@ void clock_exit_limp(void) ; }
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X void setup_5441x_clocks(void) { ccm_t *ccm = (ccm_t *)MMAP_CCM; @@ -125,7 +125,7 @@ void setup_5441x_clocks(void) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X setup_5441x_clocks(); #endif
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index a083c3d45d2..baf39127b29 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -167,7 +167,7 @@ asm_dram_init: #endif #endif /* CONFIG_CF_SBF */
-#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X /* TC: enable all peripherals, in the future only enable certain peripherals */ move.l #0xFC04002D, %a1 @@ -175,7 +175,7 @@ asm_dram_init: #if defined(CONFIG_CF_SBF) move.b #23, (%a1) /* dspi */ #endif -#endif /* CONFIG_MCF5441x */ +#endif /* CONFIG_MCF5441X */
/* mandatory board level ddr-sdram init, * for both 5441x and 5445x @@ -193,7 +193,7 @@ asm_dram_init: */ /* Enable pins for DSPI mode - chip-selects are enabled later */ asm_dspi_init: -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X move.l #0xEC09404E, %a1 move.l #0xEC09404F, %a2 move.b #0xFF, (%a1) @@ -205,7 +205,7 @@ asm_dspi_init: move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0 -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X move.l #0x3E000016, (%a0) #endif
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 4acd677c676..52d12a68144 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -19,7 +19,7 @@ #define CFG_CF_V3 #endif
-#if defined(CONFIG_MCF5441x) +#if defined(CONFIG_MCF5441X) #define CFG_CF_V4E /* Four Extra ACRn */ #endif
@@ -94,7 +94,7 @@ #define CF_CACR_IDSP (1 << 7) #define CF_CACR_EUSP (1 << 5)
-#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x) +#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441X) #define CF_CACR_IVO (1 << 20) #define CF_CACR_SPA (1 << 14) #else diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 273e843c4ae..d63fb8130c4 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -20,7 +20,7 @@ struct arch_global_data { unsigned long vco_clk; unsigned long flb_clk; #endif -#ifdef CONFIG_MCF5441x +#ifdef CONFIG_MCF5441X unsigned long sdhc_clk; #endif }; diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h index 708d0db755a..1beb14ad53b 100644 --- a/arch/m68k/include/asm/immap_5441x.h +++ b/arch/m68k/include/asm/immap_5441x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * MCF5441x Internal Memory Map + * MCF5441X Internal Memory Map * * Copyright 2010-2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 66caf683f74..da888885474 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -383,7 +383,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, return 0; }
-#if IS_ENABLED(CONFIG_MCF5441x) +#if IS_ENABLED(CONFIG_MCF5441X) /* * Swaps 32-bit words to little-endian byte order. */ @@ -553,7 +553,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, dma_unmap_single(priv->dma_addr, data->blocks * data->blocksize, mmc_get_dma_dir(data)); - if (IS_ENABLED(CONFIG_MCF5441x) && + if (IS_ENABLED(CONFIG_MCF5441X) && (data->flags & MMC_DATA_READ)) sd_swap_dma_buff(data); } @@ -1026,7 +1026,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
/* Put the PROCTL reg back to the default */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD); else esdhc_write32(®s->proctl, PROCTL_INIT); @@ -1168,7 +1168,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, return ret;
/* ColdFire, using SDHC_DATA[3] for card detection */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) esdhc_write32(®s->proctl, PROCTL_INIT | PROCTL_D3CD);
if (IS_ENABLED(CONFIG_FSL_USDHC)) { @@ -1194,11 +1194,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, caps = esdhc_read32(®s->hostcapblt);
/* - * MCF5441x RM declares in more points that sdhc clock speed must + * MCF5441X RM declares in more points that sdhc clock speed must * never exceed 25 Mhz. From this, the HS bit needs to be disabled * from host capabilities. */ - if (IS_ENABLED(CONFIG_MCF5441x)) + if (IS_ENABLED(CONFIG_MCF5441X)) caps &= ~HOSTCAPBLT_HSS;
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))