On 5/2/2013 10:58 PM, Dirk Behme wrote:
Do you want to say you propose
post_div = pre_div / 16; pre_div = 16;
?
yes, that's what I said
If so:
First, I agree that we have to use the same dividers in both lines.
But, second, this would mean that you use /16 as max pre_div. For the i.MX6 case where clk_src is 60MHz this would result in a pre-divided clock of 3.75Mhz (instead of 4MHz with /15).
That does sound better for i.MX6, what about other processors using this file?
So using /15 or /16 is just a decision of which end clocks most probably are needed.
If you want to be able to configure 4MHz, 2MHz, 1MHz, 500kHz etc then /15 is the better choice.
If you want to be able to configure 3.75Mhz, 1.875MHz, 937.5kHz, 468.75kHz etc then /16 is the better choice.
I vote for /15 as done by my patch.
Thanks for explaining. The downside of using /15 is that you can't get the slowest clock possible. How about restructuring the code to improve both. Calculate post_div first.
pre_div = DIV_ROUND_UP(clk_src, max_hz); /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */ post_div = fls(pre_div - 1); if (post_div > 4) post_div -= 4; else post_div = 0;
if (post_div >= 16) { printf("Error: no divider for the freq: %d\n", max_hz); return -1; } pre_div = (pre_div + (1 << post_div) - 1) >> post_div; _________________________ Checking values for largest divisor possible (16 << 15) = (1<<19) gives post_div = 15; pre_div = 16;
Checking 1st illegal divisor (0x80001) gives post_div = 16;
Checking divisor 0xe0 gives post_div = 4; pre_div = 0xe;
Checking divisor 0xe1 gives post_div = 4; pre_div = 0xf;
Checking divisor 0x100 gives post_div = 4; pre_div = 0x10;
Checking divisor 0x101 gives post_div = 5; pre_div = 9; _________________________________________ Code is simpler and more accurate
Troy