On 01/21/2015 01:29 AM, Minghuan Lian wrote:
LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout.
VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\| |\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\| ------- <---- 4GB DDR0 space end
Signed-off-by: Minghuan Lian Minghuan.Lian@freescale.com
Applied to u-boot-fsl-qoriq master branch, awaiting upstream.
York