Hi All,
Please ignore this patch, rev1.0 will not be production.
Thanks, Zhiqiang
-----Original Message----- From: Z.q. Hou Sent: 2019年3月11日 10:59 To: u-boot@lists.denx.de; bmeng.cn@gmail.com; albert.u.boot@aribaud.net; Priyanka Jain priyanka.jain@nxp.com; York Sun york.sun@nxp.com; sriram.dash@nxp.com; yamada.masahiro@socionext.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Mingkai Hu mingkai.hu@nxp.com; M.h. Lian minghuan.lian@nxp.com Cc: Z.q. Hou zhiqiang.hou@nxp.com Subject: [PATCHv4 12/12] pci: ls_pcie_g4: add Workaround for A-011452
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
For PCIe controllers with SRIOV, MSIx table entries of all the VFs are not accessible if BAR size is set to less than 8MB.
This ERRATA is only for LX2160A Rev1.0 and will be fixed in Rev2.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V4:
- No change
drivers/pci/pcie_layerscape_gen4.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index b530a9979c..3792dbdf55 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -378,6 +378,11 @@ static void ls_pcie_g4_ep_set_bar_size(struct ls_pcie_g4 *pcie, int pf, u32 mask_l = lower_32_bits(~(size - 1)); u32 mask_h = upper_32_bits(~(size - 1));
- /* A-011452 workaround: set the VF BAR1 to 8MB */
- if (pcie->rev == REV_1_0 && vf_bar && bar == 1) {
mask_l = lower_32_bits(~(SZ_8M - 1));mask_h = upper_32_bits(~(SZ_8M - 1));- } ccsr_writel(pcie, GPEX_BAR_SELECT, bar_pos); ccsr_writel(pcie, GPEX_BAR_SIZE_LDW, mask_l); ccsr_writel(pcie, GPEX_BAR_SIZE_UDW, mask_h);
-- 2.17.1