24 Apr
2014
24 Apr
'14
12:01 a.m.
On 04/06/2014 08:16 PM, Nikhil Badola wrote:
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: Ramneek Mehresh ramneek.mehresh@freescale.com Signed-off-by: Nikhil Badola nikhil.badola@freescale.com
Applied to u-boot-mpc85xx/master, thanks.
York